公开(公告)号：US20230178426A1

公开(公告)日：2023-06-08

申请号：US17541976

申请日：2021-12-03

Applicant: Intel Corporation

Inventor： Tiffany ZINK ,  Shashi VYAS ,  Weimin HAN ,  Sudipto NASKAR ,  Charles H. WALLACE

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76834 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76844 ,  H01L23/5226 ,  H01L21/76877 ,  H01L23/53228

Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer over a conductive interconnect line, the ILD layer having a trench therein, the trench exposing a portion of the conductive interconnect line. A dielectric liner layer is along a top surface of the ILD layer and along sidewalls of the trench, the dielectric liner layer having an opening therein, the opening over the portion of the conductive interconnect line. A conductive via structure is in the trench and between portions of the dielectric liner layer along the sidewalls of the trench, the conductive via structure having a portion extending vertically beneath the dielectric liner layer and in contact with the portion of the conductive interconnect line.

公开(公告)号：US20220140069A1

公开(公告)日：2022-05-05

申请号：US17578839

申请日：2022-01-19

Applicant: Intel Corporation

Inventor： Sudipto NASKAR ,  Manish CHANDHOK ,  Abhishek A. SHARMA ,  Roman CAUDILLO ,  Scott B. CLENDENNING ,  Cheyun LIN

IPC: H01L49/02 ,  H01L27/108

Abstract: Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20220140068A1

公开(公告)日：2022-05-05

申请号：US17578043

申请日：2022-01-18

Applicant: Intel Corporation

Inventor： Sudipto NASKAR ,  Manish CHANDHOK ,  Abhishek A. SHARMA ,  Roman CAUDILLO ,  Scott B. CLENDENNING ,  Cheyun LIN

IPC: H01L49/02 ,  H01L27/108

Abstract: Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20240332166A1

公开(公告)日：2024-10-03

申请号：US18129873

申请日：2023-04-02

Applicant: Intel Corporation

Inventor： Seda CEKLI ,  Sudipto NASKAR ,  Ananya DUTTA ,  Supanee SUKRITTANON ,  Akshit PEER ,  Navneethakrishnan SALIVATI ,  Jeffery BIELEFELD ,  Makram ABD EL QADER ,  Mauro J. KOBRINSKY ,  Sachin VAIDYA

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53295

Abstract: Integrated circuit structures having air gaps are described. In an example, an integrated circuit structure includes alternating conductive lines and air gaps above a first dielectric layer. A dielectric structure is between adjacent ones of the conductive lines and over the air gaps. A first etch stop layer is on the dielectric structure but not on the conductive lines. A second etch stop layer is on the first etch stop layer and on the conductive lines. A second dielectric layer is above the second etch stop layer. A conductive via structure is in the second dielectric layer, in the second etch stop layer, and on one of the conductive lines.

公开(公告)号：US20240213250A1

公开(公告)日：2024-06-27

申请号：US18088547

申请日：2022-12-24

Applicant: INTEL CORPORATION

Inventor： Shao Ming KOH ,  Sudipto NASKAR ,  Leonard P. GULER ,  Patrick MORROW ,  Richard E. SCHENKER ,  Walid M. HAFEZ ,  Charles H. WALLACE ,  Mohit K. HARAN ,  Jeanne L. LUCE ,  Dan S. LAVRIC ,  Jack T. KAVALIEROS ,  Matthew PRINCE ,  Lars LIEBMANN

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L27/0924 ,  H01L29/0673 ,  H01L29/78696

Abstract: Embodiments disclosed herein include forksheet transistor transistors with self-aligned backbones. In an example, an integrated circuit structure includes a backbone including a lower backbone portion distinct from an upper backbone portion. A first vertical stack of nanowires is in lateral contact with a first side of the backbone. A second vertical stack of nanowires is in lateral contact with a second side of the backbone, the second side opposite the first side.

公开(公告)号：US20240120335A1

公开(公告)日：2024-04-11

申请号：US18390952

申请日：2023-12-20

Applicant: Intel Corporation

Inventor： Sudipto NASKAR ,  Biswajeet GUHA ,  William HSU ,  Bruce BEATTIE ,  Tahir GHANI

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02175 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Gate-all-around integrated circuit structures fabricated using alternate etch selective material, and the resulting structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is over the vertical arrangement of horizontal nanowires. A pair of dielectric spacers is along sides of the gate stack and over the vertical arrangement of horizontal nanowires. A metal oxide material is between adjacent ones of the vertical arrangement of horizontal nanowires at a location between the pair of dielectric spacers and the sides of the gate stack.

公开(公告)号：US20220199760A1

公开(公告)日：2022-06-23

申请号：US17129875

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Abhishek A. SHARMA ,  Noriyuki SATO ,  Sudarat LEE ,  Scott B. CLENDENNING ,  Sudipto NASKAR ,  Manish CHANDHOK ,  Hui Jae YOO ,  Van H. LE

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/528 ,  H01G4/10

Abstract: An integrated circuit (IC) structure having a plurality of backend double-walled capacitors (DWCs) are described. In an example, a first interconnect layer is disposed over a substrate and a second interconnect layer is disposed over the first interconnect layer. In the example, a plurality of DWCs are disposed in the first interconnect layer or the second interconnect layer to provide capacitance to assist the first interconnect layer and the second interconnect layer in providing electrical signal routing and power distribution to one or more devices in the IC structure. In examples, the IC structure includes a logic IC or a coupling substrate.

公开(公告)号：US20210202479A1

公开(公告)日：2021-07-01

申请号：US16727355

申请日：2019-12-26

Applicant: Intel Corporation

Inventor： Sudipto NASKAR ,  Biswajeet GUHA ,  William HSU ,  Bruce BEATTIE ,  Tahir GHANI

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08

Abstract: Gate-all-around integrated circuit structures fabricated using alternate etch selective material, and the resulting structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is over the vertical arrangement of horizontal nanowires. A pair of dielectric spacers is along sides of the gate stack and over the vertical arrangement of horizontal nanowires. A metal oxide material is between adjacent ones of the vertical arrangement of horizontal nanowires at a location between the pair of dielectric spacers and the sides of the gate stack.