公开(公告)号：US20190279978A1

公开(公告)日：2019-09-12

申请号：US15754709

申请日：2015-09-25

Applicant: INTEL CORPORATION

Inventor： RISHABH MEHANDRU ,  TAHIR GHANI ,  SZUYA S. LIAO ,  SEIYON KIM

IPC: H01L27/088 ,  H01L29/51 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/775

Abstract: Techniques are disclosed for forming nanowire transistor architectures in which the presence of gate material between neighboring nanowires is eliminated or otherwise reduced. In accordance with some embodiments, neighboring nanowires can be formed sufficiently proximate one another such that their respective gate dielectric layers are either: (1) just in contact with one another (e.g., are contiguous); or (2) merged with one another to provide a single, continuous dielectric layer shared by the neighboring nanowires. In some cases, a given gate dielectric layer may be of a multi-layer configuration, having two or more constituent dielectric layers. Thus, in accordance with some embodiments, the gate dielectric layers of neighboring nanowires may be formed such that one or more constituent dielectric layers are either: (1) just in contact with one another (e.g., are contiguous); or (2) merged with one another to provide a single, continuous constituent dielectric layer shared by the neighboring nanowires.

公开(公告)号：US20190109234A1

公开(公告)日：2019-04-11

申请号：US16199445

申请日：2018-11-26

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  TAHIR GHANI ,  YING PANG ,  NABIL G. MISTKAWI

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/08 ,  H01L29/06 ,  H01L27/092 ,  H01L29/167 ,  B82Y10/00 ,  H01L29/775 ,  H01L29/417 ,  H01L29/66 ,  H01L29/165 ,  H01L29/45 ,  H01L21/306 ,  H01L21/762 ,  H01L21/02 ,  H01L29/161 ,  H01L29/786

CPC classification number: H01L29/7848 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696

Abstract: Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm−3.

公开(公告)号：US20180248011A1

公开(公告)日：2018-08-30

申请号：US15754887

申请日：2015-09-25

Applicant: INTEL CORPORATION

Inventor： RISHABH MEHANDRU ,  TAHIR GHANI ,  SZUYA S. LIAO

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/306 ,  H01L21/265 ,  H01L21/324 ,  H01L21/768

CPC classification number: H01L29/41766 ,  B82Y10/00 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: Semiconductor contact architectures are provided, wherein contact metal extends into the semiconductor layer to which contact is being made, thereby increasing contact area. An offset spacer allows a relatively deep etch into the semiconductor material to be achieved. Thus, rather than just a flat horizontal surface of the semiconductor being exposed for contact area, relatively long vertical trench sidewalls and a bottom wall are exposed and available for contact area. The trench can then be filled with the desired contact metal. Doping of the semiconductor layer into which the contact is being formed can be carried out in a manner that facilitates an efficient contact trench etch process, such as by, for example, utilization of post trench etch doping or a semiconductor layer having an upper undoped region through which the contact trench etch passes and a lower doped S/D region. The offset spacer may be removed from final structure.

公开(公告)号：US20180248004A1

公开(公告)日：2018-08-30

申请号：US15753739

申请日：2015-09-18

Applicant: INTEL CORPORATION

Inventor： PRASHANT MAJHI ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  TAHIR GHANI ,  ARAVIND S. KILLAMPALLI ,  MARK R. BRAZIER ,  JAYA P. GUPTA

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/775 ,  H01L29/78 ,  H01L27/092 ,  H01L21/30

Abstract: Techniques are disclosed for deuterium-based passivation of non-planar transistor interfaces. In some cases, the techniques can include annealing an integrated circuit structure including the transistor in a range of temperatures, pressures, and times in an atmosphere that includes deuterium. In some instances, the anneal process may be performed at pressures of up to 50 atmospheres to increase the amount of deuterium that penetrates the integrated circuit structure and reaches the interfaces to be passivated. Interfaces to be passivated may include, for example, an interface between the transistor conductive channel and bordering transistor gate dielectric and/or an interface between sub-channel semiconductor and bordering shallow trench isolation oxides. Such interfaces are common locations of trap sites that may include impurities, incomplete bonds dangling bonds, and broken bonds, for example, and thus such interfaces can benefit from deuterium-based passivation to improve the performance and reliability of the transistor.

公开(公告)号：US20180158944A1

公开(公告)日：2018-06-07

申请号：US15576381

申请日：2015-06-23

Applicant: INTEL CORPORATION

Inventor： CHANDRA S. MOHAPATRA ,  ANAND S. MURTHY ,  GLENN A. GLASS ,  TAHIR GHANI ,  WILLY RACHMADY ,  JACK T. KAVALIEROS ,  GILBERT DEWEY ,  MATTHEW V. METZ ,  HAROLD W. KENNEL

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/12 ,  H01L29/775 ,  H01L29/66 ,  H01L29/205 ,  H01L27/088

CPC classification number: H01L29/785 ,  H01L21/02241 ,  H01L27/0886 ,  H01L29/1054 ,  H01L29/125 ,  H01L29/205 ,  H01L29/66795 ,  H01L29/775

Abstract: Techniques are disclosed for forming high mobility NMOS fin-based transistors having an indium-rich channel region electrically isolated from the sub-fin by an aluminum-containing layer. The aluminum aluminum-containing layer may be provisioned within an indium-containing layer that includes the indium-rich channel region, or may be provisioned between the indium-containing layer and the sub-fin. The indium concentration of the indium-containing layer may be graded from an indium-poor concentration near the aluminum-containing barrier layer to an indium-rich concentration at the indium-rich channel layer. The indium-rich channel layer is at or otherwise proximate to the top of the fin, according to some example embodiments. The grading can be intentional and/or due to the effect of reorganization of atoms at the interface of indium-rich channel layer and the aluminum-containing barrier layer. Numerous variations and embodiments will be appreciated in light of this disclosure.

公开(公告)号：US20180158841A1

公开(公告)日：2018-06-07

申请号：US15576393

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  DANIEL B. AUBERTINE ,  TAHIR GHANI ,  JACK T. KAVALIEROS ,  BENJAMIN CHU-KUNG ,  CHANDRA S. MOHAPATRA ,  KARTHIK JAMBUNATHAN ,  GILBERT DEWEY ,  WILLY RACHMADY

IPC: H01L27/12 ,  H01L29/161 ,  H01L29/20 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L27/1211 ,  H01L21/76224 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78

Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. In accordance with an embodiment, sacrificial fins are cladded and then removed thereby leaving the cladding layer as a pair of standalone fins. Once the sacrificial fin areas are filled back in with a suitable insulator, the resulting structure is fin-on-insulator. The new fins can be configured with any materials by using such a cladding-on-core approach. The resulting fin-on-insulator structure is favorable, for instance, for good gate control while eliminating or otherwise reducing sub-channel source-to-drain (or drain-to-source) leakage current. In addition, parasitic capacitance from channel-to-substrate is significantly reduced. The sacrificial fins can be thought of as cores and can be implemented, for example, with material native to the substrate or a replacement material that enables low-defect exotic cladding materials combinations.

公开(公告)号：US20180151677A1

公开(公告)日：2018-05-31

申请号：US15576150

申请日：2015-06-24

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  YING PANG ,  ANAND S. MURTHY ,  TAHIR GHANI ,  KARTHIK JAMBUNATHAN

IPC: H01L29/40 ,  H01L27/092 ,  H01L29/78 ,  H01L29/16 ,  H01L29/20 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/66

Abstract: Techniques are disclosed for reducing off-state leakage of fin-based transistors through the use of a sub-fin passivation layer. In some cases, the techniques include forming sacrificial fins in a bulk silicon substrate and depositing and planarizing shallow trench isolation (STI) material, removing and replacing the sacrificial silicon fins with a replacement material (e.g., SiGe or III-V material), removing at least a portion of the STI material to expose the sub-fin areas of the replacement fins, applying a passivating layer/treatment/agent to the exposed sub-fins, and re-depositing and planarizing additional STI material. Standard transistor forming processes can then be carried out to complete the transistor device. The techniques generally provide the ability to add arbitrary passivation layers for structures that are grown in STI-based trenches. The passivation layer inhibits sub-fin source-to-drain (and drain-to-source) current leakage.

公开(公告)号：US20170047419A1

公开(公告)日：2017-02-16

申请号：US15339308

申请日：2016-10-31

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  TAHIR GHANI

IPC: H01L29/45 ,  H01L21/768 ,  H01L29/165 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/45 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76864 ,  H01L21/76895 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

Abstract translation: 公开了用于形成相对于常规器件具有降低的寄生接触电阻的晶体管器件的技术。 这些技术可以例如使用例如硅或硅锗（SiGe）源极/漏极区域上的一系列金属的标准接触堆叠来实现。 根据这种实施例的一个示例，在源极/漏极和接触金属之间提供中间硼掺杂锗层以显着降低接触电阻。 根据本公开，包括平面和非平面晶体管结构（例如，FinFET）以及应变和非限制的通道结构，许多晶体管配置和合适的制造工艺将是显而易见的。 分级缓冲可用于减少错配错位。 这些技术特别适用于实现p型器件，但如果需要，可以用于n型器件。

公开(公告)号：US20160118384A1

公开(公告)日：2016-04-28

申请号：US14981206

申请日：2015-12-28

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  TAHIR GHANI

IPC: H01L27/092 ,  H01L29/267 ,  H01L29/78 ,  H01L23/535 ,  H01L29/417 ,  H01L29/06 ,  H01L29/165 ,  H01L29/08

CPC classification number: H01L27/0922 ,  H01L21/28185 ,  H01L21/28525 ,  H01L21/28575 ,  H01L21/76814 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/8258 ,  H01L23/535 ,  H01L27/0605 ,  H01L27/0924 ,  H01L29/0669 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/41725 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques are disclosed for forming low contact resistance transistor devices. A p-type germanium layer is provided between p-type source/drain regions and their respective contact metals, and an n-type III-V semiconductor material layer is provided between n-type source/drain regions and their respective contact metals. The n-type III-V semiconductor material layer may have a small bandgap (e.g.,

公开(公告)号：US20210083116A1

公开(公告)日：2021-03-18

申请号：US16611920

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： KARTHIK JAMBUNATHAN ,  CORY C. BOMBERGER ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  JU H. NAM ,  TAHIR GHANI

IPC: H01L29/78 ,  H01L27/092

Abstract: Techniques are disclosed for performing silicon (Si) substrate modification to enable formation of a thin, relaxed germanium (Ge)-based layer on the modified Si substrate. The thin, relaxed, Ge-based layer (e.g., having a thickness of at most 500 nm) can then serve as a template for the growth of compressively strained PMOS channel material and tensile strained NMOS channel material to achieve gains in hole and electron mobility, respectively, in the channel regions of the devices. Such a relatively thin Ge-based layer can be formed with suitable surface quality/relaxation levels due to the modification of the Si substrate, where such modification may include depositing a modification layer or performing ion implantation in/on the Si substrate. The modification layer can be characterized by the nucleation of defects which predominantly terminate within the Si substrate or the Ge-based layer, rather than running through to the top of the Ge-based layer.