公开(公告)号：US11239361B2

公开(公告)日：2022-02-01

申请号：US16640043

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Uygar E. Avci ,  Joshua M. Howard ,  Seiyon Kim ,  Ian A. Young

IPC: H01L29/78 ,  H01L49/02 ,  H01L29/51

Abstract: Described is an apparatus which comprises: a first layer comprising a semiconductor; a second layer comprising an insulating material, the second layer adjacent to the first layer; a third layer comprising a high-k insulating material, the third layer adjacent to the second layer; a fourth layer comprising a ferroelectric material, the fourth layer adjacent to the third layer; and a fifth layer comprising a high-k insulating material, the fifth layer adjacent to the fourth layer.

公开(公告)号：US20200235110A1

公开(公告)日：2020-07-23

申请号：US16640041

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

IPC: H01L27/11507 ,  H01L49/02 ,  G11C11/22

Abstract: Described is an apparatus which comprises: a word line; a source line; a bit-line; and a memory bit-cell coupled to the source line, the bit-line, and the word line, wherein the memory bit-cell comprises a capacitor including ferroelectric material and a transistor fabricated on a backend of a die.

公开(公告)号：US10720438B2

公开(公告)日：2020-07-21

申请号：US16146835

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

IPC: H01L27/11507 ,  H01L49/02 ,  H01L29/78 ,  H01L25/18 ,  H01L25/065 ,  H01L23/367 ,  H01L23/00 ,  H01L23/16

Abstract: An embodiment includes a system comprising: first, second, and third word lines on a semiconductor material; first, second, and third channels; first, second, and third capacitors including a ferroelectric material; a bit line; first, second, third, fourth, and fifth semiconductor nodes, wherein the first semiconductor node couples the first capacitor to the first channel, the second semiconductor node couples the bit line to the first channel; the third semiconductor node couples the second capacitor to the second channel, the fourth semiconductor node couples the third capacitor to the third channel, and the fifth semiconductor node couples the bit line to the third channel; wherein the first channel has a long axis and a short axis; wherein the long axis intersects a continuous, uninterrupted portion of the semiconductor material from the first channel to the third channel.

公开(公告)号：US20200152781A1

公开(公告)日：2020-05-14

申请号：US16631059

申请日：2017-09-12

Applicant: INTEL CORPORATION

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Uygar E. Avci ,  Christopher J. Wiegand ,  Anurag Chaudhry ,  Jasmeet S. Chawla ,  Ian A. Young

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/49 ,  H01L29/08 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  H01L29/417

Abstract: Techniques are disclosed for forming semiconductor integrated circuits including one or more of source and drain contacts and gate electrodes comprising crystalline alloys including a transition metal. The crystalline alloys help to reduce contact resistance to the semiconductor devices. In some embodiments of the present disclosure, this reduction in contact resistance is accomplished by aligning the work function of the crystalline alloy with the work function of the source and drain regions such that a Schottky barrier height associated with an interface between the crystalline alloys and the source and drain regions is in a range of 0.3 eV or less.

公开(公告)号：US20200105771A1

公开(公告)日：2020-04-02

申请号：US16146835

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

IPC: H01L27/11507 ,  H01L49/02 ,  H01L29/78 ,  H01L25/18 ,  H01L25/065 ,  H01L23/16 ,  H01L23/367 ,  H01L23/00

Abstract: An embodiment includes a system comprising: first, second, and third word lines on a semiconductor material; first, second, and third channels; first, second, and third capacitors including a ferroelectric material; a bit line; first, second, third, fourth, and fifth semiconductor nodes, wherein the first semiconductor node couples the first capacitor to the first channel, the second semiconductor node couples the bit line to the first channel; the third semiconductor node couples the second capacitor to the second channel, the fourth semiconductor node couples the third capacitor to the third channel, and the fifth semiconductor node couples the bit line to the third channel; wherein the first channel has a long axis and a short axis; wherein the long axis intersects a continuous, uninterrupted portion of the semiconductor material from the first channel to the third channel.

公开(公告)号：US20200075609A1

公开(公告)日：2020-03-05

申请号：US16114272

申请日：2018-08-28

Applicant: Intel Corporation

Inventor： Daniel H. Morris ,  Seiyon Kim ,  Uygar E. Avci ,  Ian A. Young

IPC: H01L27/1159 ,  H01L29/51 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  G11C11/22

Abstract: Described herein are ferroelectric (FE) memory cells that include transistors having gates with FE capacitors integrated therein. An example memory cell includes a transistor having a semiconductor channel material, a gate dielectric over the semiconductor material, a first conductor material over the gate dielectric, a FE material over the first conductor material, and a second conductor material over the FE material. The first and second conductor materials form, respectively, first and second capacitor electrodes of a capacitor, where the first and second capacitor electrodes are separated by the FE material (hence, a “FE capacitor”). Separating a FE material from a semiconductor channel material of a transistor with a layer of a gate dielectric and a layer of a first conductor material eliminates the FE-semiconductor interface that may cause endurance issues in some other FE memory cells.

公开(公告)号：US20190386661A1

公开(公告)日：2019-12-19

申请号：US15779074

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Ian A. Young ,  Dmitri E. Nikonov ,  Uygar E. Avci ,  Patrick Morrow ,  Anurag Chaudhry

IPC: H03K19/00 ,  H03K19/18 ,  H01L43/04 ,  H01L43/06 ,  H01L43/10

Abstract: Described is an apparatus which comprises: a 4-state input magnet; a first spin channel region adjacent to the 4-state input magnet; a 4-state output magnet; a second spin channel region adjacent to the 4-state input and output magnets; and a third spin channel region adjacent to the 4-state output magnet. Described in an apparatus which comprises: a 4-state input magnet; a first filter layer adjacent to the 4-state input magnet; a first spin channel region adjacent to the first filter layer; a 4-state output magnet; a second filter layer adjacent to the 4-state output magnet; a second spin channel region adjacent to the first and second filter layers; and a third spin channel region adjacent to the second filter layer.

公开(公告)号：US09583566B2

公开(公告)日：2017-02-28

申请号：US14942274

申请日：2015-11-16

Applicant: Intel Corporation

Inventor： Uygar E. Avci ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: H01L29/06 ,  H01L29/772 ,  H01L29/267 ,  H01L29/739 ,  H01L29/165 ,  H01L29/205 ,  H01L29/08 ,  H01L29/10 ,  H01L29/775 ,  B82Y10/00

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L29/068 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/205 ,  H01L29/267 ,  H01L29/7391 ,  H01L29/772 ,  H01L29/775

Abstract: An embodiment includes a heterojunction tunneling field effect transistor including a source, a channel, and a drain; wherein (a) the channel includes a major axis, corresponding to channel length, and a minor axis that corresponds to channel width and is orthogonal to the major axis; (b) the channel length is less than 10 nm long; (c) the source is doped with a first polarity and has a first conduction band; (d) the drain is doped with a second polarity, which is opposite the first polarity, and the drain has a second conduction band with higher energy than the first conduction band. Other embodiments are described herein.

Abstract translation: 一个实施例包括一个包括源极，沟道和漏极的异质结隧道场效应晶体管; 其中（a）所述通道包括对应于通道长度的长轴和对应于通道宽度并与所述长轴正交的短轴; （b）通道长度小于10nm; （c）源极掺杂第一极性并具有第一导带; （d）漏极掺杂有与第一极性相反的第二极性，并且漏极具有比第一导带具有更高能量的第二导带。 本文描述了其它实施例。

公开(公告)号：US09412872B2

公开(公告)日：2016-08-09

申请号：US14521200

申请日：2014-10-22

Applicant: Intel Corporation

Inventor： Roza Kotlyar ,  Stephen M. Cea ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Uygar E. Avci ,  Rafael Rios ,  Anurag Chaudhry ,  Thomas D. Linton, Jr. ,  Ian A. Young ,  Kelin J. Kuhn

IPC: H01L29/78 ,  H01L29/739 ,  H01L29/16 ,  H01L29/161 ,  H01L29/06 ,  H01L29/24 ,  H01L29/267

CPC classification number: H01L29/66977 ,  H01L27/092 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/24 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/7391 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78642 ,  H01L29/78684 ,  H01L29/78696

Abstract: Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.

Abstract translation: 描述了用于CMOS架构的隧道场效应晶体管（TFET）和制造N型和P型TFET的方法。 例如，隧道场效应晶体管（TFET）包括设置在衬底上方的均质有源区。 同质结有源区包括其中具有未掺杂沟道区的松弛Ge或GeSn体。 同质结有源区还包括设置在放大的Ge或GeSn体中，在沟道区两侧的掺杂源极和漏极区。 TFET还包括设置在沟道区域之间的源极和漏极区域之间的栅极堆叠。 栅极堆叠包括栅极电介质部分和栅极电极部分。

公开(公告)号：US09209288B2

公开(公告)日：2015-12-08

申请号：US13723634

申请日：2012-12-21

Applicant: Intel Corporation

Inventor： Uygar E. Avci ,  Dmitri Nikonov ,  Ian Young

IPC: H01L29/772 ,  H01L29/267 ,  H01L29/739 ,  H01L29/165 ,  H01L29/205 ,  B82Y10/00 ,  H01L29/06

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L29/068 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/205 ,  H01L29/267 ,  H01L29/7391 ,  H01L29/772 ,  H01L29/775

Abstract: An embodiment includes a heterojunction tunneling field effect transistor including a source, a channel, and a drain; wherein (a) the channel includes a major axis, corresponding to channel length, and a minor axis that corresponds to channel width and is orthogonal to the major axis; (b) the channel length is less than 10 nm long; (c) the source is doped with a first polarity and has a first conduction band; (d) the drain is doped with a second polarity, which is opposite the first polarity, and the drain has a second conduction band with higher energy than the first conduction band. Other embodiments are described herein.

Abstract translation: 一个实施例包括一个包括源极，沟道和漏极的异质结隧道场效应晶体管; 其中（a）所述通道包括对应于通道长度的长轴和对应于通道宽度并与所述长轴正交的短轴; （b）通道长度小于10nm; （c）源极掺杂第一极性并具有第一导带; （d）漏极掺杂有与第一极性相反的第二极性，并且漏极具有比第一导带具有更高能量的第二导带。 本文描述了其它实施例。