公开(公告)号：US20190036002A1

公开(公告)日：2019-01-31

申请号：US16072166

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Shawna M. LIFF ,  Feras EID ,  Aleksandar ALEKSOV ,  Sasha N. OSTER ,  Baris BICEN ,  Thomas L. SOUNART ,  Johanna M. SWAN ,  Adel A. ELSHERBINI ,  Valluri R. RAO

IPC: H01L41/09 ,  G02F1/01 ,  H01L27/32 ,  F21S10/02 ,  H01L41/22 ,  H01L51/00

Abstract: Embodiments of the invention include piezoelectrically driven switches that are used for modifying a background color or light source color in display systems, and methods of forming such devices. In an embodiment, a piezoelectrically actuated switch for modulating a background color in a display may include a photonic crystal that has a plurality of blinds oriented substantially perpendicular to a surface of the display. In an embodiment, the blinds include a black surface and a white surface. The switch may also include an anchor spaced away from an edge of the photonic crystal and a piezoelectric actuator formed on the surface of the anchor and a surface of the photonic crystal. Some embodiments may include a photonic crystal that is a multi-layer polymeric structure or a polymer chain with a plurality of nanoparticles spaced at regular intervals on the polymer chain.

公开(公告)号：US20190033500A1

公开(公告)日：2019-01-31

申请号：US16072173

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Thomas L. SOUNART ,  Baris BICEN ,  Feras EID ,  Sasha N. OSTER ,  Aleksandar ALEKSOV ,  Shawna M. LIFF ,  Valluri R. RAO ,  Johanna M. SWAN

IPC: G02B5/18 ,  G02B26/08 ,  H01L41/09

Abstract: Embodiments of the invention include an optical grating switch integrated into an organic substrate and methods of forming such devices. According to an embodiment, the optical grating switch may include a cavity formed into an organic substrate. Additionally, the optical grating switch may include an array of moveable beams anchored to the organic substrate and suspended over the cavity. In an embodiment of the invention, each of the moveable beams in the optical grating switch may include a piezoelectric region formed over end portions of the moveable beam and a top electrode formed over a top surface of each of the piezoelectric regions. In order to reflect or diffract light, embodiments of the invention may include moveable beams that include a reflective surface formed over a central portion of the moveable beam.

公开(公告)号：US20170011912A1

公开(公告)日：2017-01-12

申请号：US15119683

申请日：2014-03-18

Applicant: INTEL CORPORATION

Inventor： Niloy MUKHERJEE ,  Brian S. DOYLE ,  Marko RADOSAVLJEVIC ,  Ravi PILLARISETTY ,  Han Wui THEN ,  Valluri R. RAO ,  Robert S. CHAU

IPC: H01L21/02 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L21/02513 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/02282 ,  H01L21/02422 ,  H01L21/02428 ,  H01L21/02488 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02549 ,  H01L21/02551 ,  H01L21/02595 ,  H01L21/02631 ,  H01L21/02675 ,  H01L21/763 ,  H01L27/1218 ,  H01L27/1225 ,  H01L29/78603 ,  H01L29/78681

Abstract: Embodiments of semiconductor assemblies, and related integrated circuit devices and techniques, are disclosed herein. In some embodiments, a semiconductor assembly may include a flexible substrate, a polycrystalline semiconductor material, and a polycrystalline dielectric disposed between and adjacent to the flexible substrate and the polycrystalline semiconductor material. The polycrystalline semiconductor material. The polycrystalline semiconductor material may include a polycrystalline III-V material, a polycrystalline II-VI material or polycrystalline germanium. Other embodiments may be disclosed and/or claimed.

Abstract translation: 本文公开了半导体组件的实施例以及相关的集成电路器件和技术。 在一些实施例中，半导体组件可以包括柔性衬底，多晶半导体材料和布置在柔性衬底和多晶半导体材料之间和之后的多晶电介质。 多晶半导体材料。 多晶半导体材料可以包括多晶III-V材料，多晶II-VI材料或多晶锗。 可以公开和/或要求保护其他实施例。

公开(公告)号：US20200227396A1

公开(公告)日：2020-07-16

申请号：US15754822

申请日：2015-09-24

Applicant: Intel Corporation

Inventor： Sansaptak W. DASGUPTA ,  Marko RADOSAVLJEVIC ,  Han Wui THEN ,  Ravi PILLARISETTY ,  Kimin JUN ,  Patrick MORROW ,  Valluri R. RAO ,  Paul B. FISCHER ,  Robert S. CHAU

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L21/78 ,  H01L25/00

Abstract: The electrical and electrochemical properties of various semiconductors may limit the usefulness of various semiconductor materials for one or more purposes. A completed gallium nitride (GaN) semiconductor layer containing a number of GaN power management integrated circuit (PMIC) dies may be bonded to a completed silicon semiconductor layer containing a number of complementary metal oxide (CMOS) control circuit dies. The completed GaN layer and the completed silicon layer may be full size (e.g., 300 mm). A layer transfer operation may be used to bond the completed GaN layer to the completed silicon layer. The layer transfer operation may be performed on full size wafers. After slicing the full size wafers a large number of multi-layer dies, each having a GaN die layer transferred to a silicon die may be produced.

公开(公告)号：US20190297975A1

公开(公告)日：2019-10-03

申请号：US16303386

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Sasha N. OSTER ,  Feras EID ,  Shawna M. LIFF ,  Thomas L. SOUNART ,  Johanna M. SWAN ,  Baris BICEN ,  Valluri R. RAO

IPC: A41D27/28 ,  A41D13/00 ,  A41D27/24 ,  A61M35/00 ,  A61M5/145

Abstract: Embodiments of the invention include an active venting system. According to an embodiment of the invention, the active venting system may include a substrate having one or more seams formed through the substrate. In order to open the vents defined by the seams through the substrate, a piezoelectric layer may be formed proximate to one or more of the seams. Additional embodiments may include a first electrode and a second electrode that contact the piezoelectric layer in order to provide a voltage differential across the piezoelectric layer. In an embodiment the active venting system may be integrated into a garment. In such an embodiment, the garment may also include an electronics module for controlling the actuators. Additionally, conductive traces may be printed on the garment or sewn into the garment to provide electrical connections from the electronics module to each of the piezoelectric actuators.

公开(公告)号：US20170288639A1

公开(公告)日：2017-10-05

申请号：US15088830

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Feras EID ,  Baris BICEN ,  Telesphor KAMGAING ,  Vijay K. NAIR ,  Georgios C. DOGIAMIS ,  Johanna M. SWAN ,  Valluri R. RAO

IPC: H03H9/30 ,  H03H9/13

Abstract: Embodiments of the invention include a waveguide structure that includes a first piezoelectric transducer that is positioned in proximity to a first end of a cavity of an organic substrate. The first piezoelectric transducer receives an input electrical signal and generates an acoustic wave to be transmitted with a transmission medium. A second piezoelectric transducer is positioned in proximity to a second end of the cavity. The second piezoelectric transducer receives the acoustic wave from the transmission medium and generates an output electrical signal.

公开(公告)号：US20170283249A1

公开(公告)日：2017-10-05

申请号：US15088982

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Georgios C. DOGIAMIS ,  Feras EID ,  Adel A. ELSHERBINI ,  Vijay K. NAIR ,  Telesphor KAMGAING ,  Valluri R. RAO ,  Johanna M. SWAN

IPC: B81B7/00

CPC classification number: B81C1/0015 ,  B81B2201/014 ,  B81B2203/0118 ,  B81B2203/0307 ,  B81B2203/04

Abstract: Embodiments of the invention include a switching device that includes an electrode, a piezoelectric material coupled to the electrode, and a movable structure (e.g., cantilever, beam) coupled to the piezoelectric material. The movable structure includes a first end coupled to an anchor of a package substrate having organic layers and a second released end positioned within a cavity of the package substrate.

公开(公告)号：US20160276424A1

公开(公告)日：2016-09-22

申请号：US15169665

申请日：2016-05-31

Applicant: INTEL CORPORATION

Inventor： Andreas DUEVEL ,  Telesphor KAMGAING ,  Valluri R. RAO ,  Uwe ZILLMANN

IPC: H01L49/02 ,  H01L23/48 ,  H01L27/06 ,  H01L21/768

CPC classification number: H01L28/10 ,  H01F17/0006 ,  H01F2017/002 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5227 ,  H01L27/0688 ,  H01L27/08 ,  H01L2224/4813 ,  H01L2924/0002 ,  H01L2924/00012

Abstract: A three-dimensional inductor is formed in an integrated circuit die using conductive through-body-vias which pass through the body of the die and contact one or more metal interconnect layers on the front side of the die and terminate on the back side of the die. In another embodiment, the through-body-vias may pass through a dielectric material disposed in a plug in the body of the die. In yet another aspect, a transformer may be formed by coupling multiple inductors formed using through-body-vias. In still another aspect, a three-dimensional inductor may include conductors formed of stacks of on chip metallization layers and conductive through-layer-vias disposed in insulation layers between metallization layers. Other embodiments are described.

Abstract translation: 使用导电贯穿体通孔在集成电路管芯中形成三维电感器，该穿通体通孔穿过管芯的主体并与管芯前侧上的一个或多个金属互连层接触并终止在管芯的背面 死。 在另一个实施例中，通孔通孔可以穿过设置在管芯主体中的插塞中的电介质材料。 另一方面，变压器可以通过耦合使用通孔通孔形成的多个电感器来形成。 在另一方面，三维电感器可以包括由片上金属化层的堆叠形成的导体和设置在金属化层之间的绝缘层中的导电贯通层通孔。 描述其他实施例。

公开(公告)号：US20200035560A1

公开(公告)日：2020-01-30

申请号：US16316330

申请日：2017-08-25

Applicant: Intel Corporation

Inventor： Bruce BLOCK ,  Valluri R. RAO ,  Patrick MORROW ,  Rishabh MEHANDRU ,  Doug INGERLY ,  Kimin JUN ,  Kevin O'BRIEN ,  Patrick MORROW ,  Szyua S. LIAO

IPC: H01L21/822 ,  H01L29/04 ,  H01L29/08 ,  H01L23/528 ,  H01L23/00 ,  H01L29/16 ,  H01L29/20 ,  H01L27/092 ,  H01L27/12 ,  H01L23/532 ,  H01L21/8238 ,  H01L21/306 ,  H01L21/683 ,  H01L29/06 ,  H01L21/66

Abstract: Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.

公开(公告)号：US20190121038A1

公开(公告)日：2019-04-25

申请号：US16098406

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Johanna M. SWAN ,  Aleksandar ALEKSOV ,  Sasha N. OSTER ,  Feras EID ,  Baris BICEN ,  Thomas L. SOUNART ,  Shawna M. LIFF ,  Valluri R. RAO

IPC: G02B6/42

Abstract: Embodiments of the invention include an optoelectronic package that allows for in situ alignment of optical fibers. In an embodiment, the optoelectronic package may include an organic substrate. Embodiments include a cavity formed into the organic substrate. Additionally, the optoelectronic package may include an actuator formed on the organic substrate that extends over the cavity. In one embodiment, the actuator may include a first electrode, a piezoelectric layer formed on the first electrode, and a second electrode formed on the piezoelectric layer. According to an additional embodiment of the invention, the actuator may include a first portion and a second portion. In order to allow for resistive heating and actuation driven by thermal expansion, a cross-sectional area of the first portion of the beam may be greater than a cross-sectional area of the second portion of the beam.