公开(公告)号：US20190025573A1

公开(公告)日：2019-01-24

申请号：US16072164

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Feras EID ,  Sasha N. OSTER ,  Shawna M. LIFF ,  Johanna M. SWAN ,  Thomas L. SOUNART ,  Baris BICEN ,  Valluri R. RAO

IPC: G02B26/10 ,  G02B26/08

Abstract: Embodiments of the invention include maskless imaging tools and display systems that include piezoelectrically actuated mirrors and methods of forming such devices. According to an embodiment, the maskless imaging tool may include a light source. Additionally, the tool may include one or more piezoelectrically actuated mirrors for receiving light from the light source. In an embodiment, the piezoelectrically actuated mirrors are actuatable about one or more axes to reflect the light from the light source to a workpiece positioned to receive light from the piezoelectrically actuated mirror. Additional embodiments of the invention may include a maskless imaging tool that is a laser direct imaging lithography (LDIL) tool. Other embodiments may include a maskless imaging tool that is a via-drill tool. Embodiments of the invention may also include a piezoelectrically actuated mirror used in a projection system. For example, the projection system may be integrated into a pair of glasses.

公开(公告)号：US20170309700A1

公开(公告)日：2017-10-26

申请号：US15589981

申请日：2017-05-08

Applicant: INTEL CORPORATION

Inventor： Andreas DUEVEL ,  Telesphor KAMGAING ,  Valluri R. RAO ,  Uwe ZILLMANN

IPC: H01L49/02 ,  H01L21/768 ,  H01L27/06 ,  H01F17/00 ,  H01L23/522 ,  H01L23/48 ,  H01L27/08

CPC classification number: H01L28/10 ,  H01F17/0006 ,  H01F2017/002 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5227 ,  H01L27/0688 ,  H01L27/08 ,  H01L2224/4813 ,  H01L2924/0002 ,  H01L2924/00012

Abstract: A three-dimensional inductor is formed in an integrated circuit die using conductive through-body-vias which pass through the body of the die and contact one or more metal interconnect layers on the front side of the die and terminate on the back side of the die. In another embodiment, the through-body-vias may pass through a dielectric material disposed in a plug in the body of the die. In yet another aspect, a transformer may be formed by coupling multiple inductors formed using through-body-vias. In still another aspect, a three-dimensional inductor may include conductors formed of stacks of on chip metallization layers and conductive through-layer-vias disposed in insulation layers between metallization layers. Other embodiments are described.

公开(公告)号：US20170288724A1

公开(公告)日：2017-10-05

申请号：US15088996

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Telesphor KAMGAING ,  Feras EID ,  Adel A. ELSHERBINI ,  Georgios C. DOGIAMIS ,  Vijay K. NAIR ,  Johanna M. SWAN ,  Valluri R. RAO

IPC: H04B1/48 ,  H03H9/05 ,  H03H9/54 ,  H01H57/00

CPC classification number: H04B1/48 ,  H01H57/00 ,  H01H2057/006 ,  H03H7/38 ,  H03H2015/005

Abstract: Embodiments of the invention include a tunable radio frequency (RF) communication module that includes a transmitting component having at least one tunable component and a receiving component having at least one tunable component. The tunable RF communication module includes at least one piezoelectric switching device coupled to at least one of the transmitting and receiving components. The at least one piezoelectric switching device is formed within an organic substrate having organic material and is designed to tune at least one tunable component of the tunable RF communication module.

公开(公告)号：US20200064555A1

公开(公告)日：2020-02-27

申请号：US16072240

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Sasha N. OSTER ,  Johanna M. SWAN ,  Feras EID ,  Thomas L. SOUNART ,  Aleksandar ALEKSOV ,  Shawna M. LIFF ,  Baris BICEN ,  Valluri R. RAO

IPC: G02B6/35 ,  H04Q11/00 ,  H04B10/25

Abstract: Embodiments of the invention include an optical routing device that includes an organic substrate. According to an embodiment, an array of cavities are formed into the organic substrate and an array of piezoelectrically actuated mirrors may be anchored to the organic substrate with each piezoelectrically actuated mirror extending over a cavity. In order to properly rout incoming optical signals, the optical routing device may also include a routing die mounted on the organic substrate. The routing die may be electrically coupled to each of the piezoelectrically actuated mirrors and is able to generated a voltage across the first and second electrodes of each piezoelectrically actuated mirror. Additionally, a photodetector may be electrically coupled to the routing die. According to an embodiment, an array of fiber optic cables may be optically coupled with one of the piezoelectrically actuated mirrors and optically coupled with the photodetector.

公开(公告)号：US20190036004A1

公开(公告)日：2019-01-31

申请号：US16071992

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Feras EID ,  Sasha N. OSTER ,  Shawna M. LIFF ,  Johanna M. SWAN ,  Thomas L. SOUNART ,  Aleksandar ALEKSOV ,  Valluri R. RAO ,  Baris BICEN

IPC: H01L41/113 ,  H01L41/047 ,  H01L41/253 ,  H01L41/29 ,  H01L41/316 ,  H01L41/332 ,  H01L41/317 ,  H01L27/20 ,  G01L1/16

Abstract: Embodiments of the invention include a piezoelectric sensor system. According to an embodiment of the invention, the piezoelectric sensor system may include a piezoelectric sensor, a signal conditioning circuit, and a light source each formed on an organic or flexible substrate. In embodiments of the invention, the piezoelectric sensor may be a discrete component or the piezo electric sensor may be integrated into the substrate. According to an embodiment, a piezoelectric sensor that is integrated into the substrate may comprise, a cavity formed into the organic substrate and a moveable beam formed over the cavity and anchored to the organic substrate. Additionally, the piezoelectric sensor may include a piezoelectric region formed over an end portion of the moveable beam and extending at least partially over the cavity. The piezoelectric sensor may also include a top electrode formed over a top surface of the piezoelectric region.

公开(公告)号：US20170288635A1

公开(公告)日：2017-10-05

申请号：US15088814

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Feras EID ,  Baris BICEN ,  Telesphor KAMGAING ,  Vijay K. NAIR ,  Johanna M. SWAN ,  Georgios C. DOGIAMIS ,  Valluri R. RAO

IPC: H03H9/02 ,  H03H9/17

CPC classification number: H03H9/02259 ,  H03H9/17 ,  H03H9/2463 ,  H03H2009/02291 ,  H03H2009/155

Abstract: Embodiments of the invention include a piezoelectric resonator which includes an input transducer having a first piezoelectric material, a vibrating structure coupled to the input transducer, and an output transducer coupled to the vibrating structure. In one example, the vibrating structure is positioned above a cavity of an organic substrate. The output transducer includes a second piezoelectric material. In operation the input transducer causes an input electrical signal to be converted into mechanical vibrations which propagate across the vibrating structure to the output transducer.

公开(公告)号：US20170286731A1

公开(公告)日：2017-10-05

申请号：US15586820

申请日：2017-05-04

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Telesphor KAMGAING ,  Feras EID ,  Vijay K. NAIR ,  Georgios C. DOGIAMIS ,  Johanna M. SWAN ,  Valluri R. RAO

IPC: G06K7/10 ,  H03H9/17 ,  H03H9/205 ,  H03H9/30

CPC classification number: G06K7/10297 ,  G06K7/10316 ,  G06K19/0672 ,  G06K19/0675 ,  H03H9/30

Abstract: Embodiments of the invention include delay line circuitry that is integrated with an organic substrate. Organic dielectric material and a plurality of conductive layers form the organic substrate. The delay line circuitry includes a piezoelectric transducer to receive a guided electromagnetic wave signal and to generate an acoustic wave signal to be transmitted with an acoustic transmission medium. An acoustic reflector is communicatively coupled to the acoustic transmission medium. The acoustic reflector receives a plurality of acoustic wave signals from the acoustic transmission medium and reflects acoustic wave signals to the piezoelectric transducer using the acoustic transmission medium. The transducer converts the reflected acoustic signals into electromagnetic waves which are then transmitted back through the antenna and decoded by the reader.

公开(公告)号：US20240194533A1

公开(公告)日：2024-06-13

申请号：US18389625

申请日：2023-12-19

Applicant: Intel Corporation

Inventor： Valluri R. RAO ,  Patrick MORROW ,  Rishabh MEHANDRU ,  Doug INGERLY ,  Kimin JUN ,  Kevin O'BRIEN ,  Paul FISCHER ,  Szuya S. LIAO ,  Bruce BLOCK

IPC: H01L21/822 ,  G01R1/073 ,  H01L21/306 ,  H01L21/66 ,  H01L21/683 ,  H01L21/8238 ,  H01L23/00 ,  H01L23/528 ,  H01L23/532 ,  H01L25/065 ,  H01L27/092 ,  H01L27/12 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L21/8221 ,  H01L21/30625 ,  H01L21/6835 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L22/14 ,  H01L23/528 ,  H01L23/53233 ,  H01L24/03 ,  H01L24/05 ,  H01L27/0924 ,  H01L27/1207 ,  H01L29/04 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/20 ,  G01R1/07307 ,  H01L24/08 ,  H01L25/0657 ,  H01L27/1214 ,  H01L27/1222 ,  H01L29/66545 ,  H01L2221/68345 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/08147 ,  H01L2225/06565

Abstract: Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Electrical test may be performed from front and back sides of a workpiece. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.

公开(公告)号：US20210193613A1

公开(公告)日：2021-06-24

申请号：US16080989

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Fay HUA ,  Christopher M. PELTO ,  Valluri R. RAO ,  Mark T. BOHR ,  Johanna M. SWAN

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/78 ,  H01L21/768 ,  H01L25/00 ,  H01L21/02

Abstract: Embodiments of the present disclosure describe techniques for fabricating a stacked integrated circuit (IC) device. A first wafer that includes a plurality of first IC dies may be sorted to identify first known good dies of the plurality of first IC dies. The first wafer may be diced to singulate the first IC dies. A second wafer that includes a plurality of second IC dies may be sorted to identify second know good dies of the plurality of second IC dies. The first known good dies may be bonded to respective second known good dies of the second wafer. In some embodiments, the first known good dies may be thinned after bonding the first know good dies to the second wafer. Other embodiments may be described and/or claimed.

公开(公告)号：US20210175124A1

公开(公告)日：2021-06-10

申请号：US17112697

申请日：2020-12-04

Applicant: Intel Corporation

Inventor： Valluri R. RAO ,  Patrick MORROW ,  Rishabh MEHANDRU ,  Doug INGERLY ,  Kimin JUN ,  Kevin O'BRIEN ,  Paul FISCHER ,  Szuya S. LIAO ,  Bruce BLOCK

IPC: H01L21/822 ,  H01L21/8238 ,  H01L27/12 ,  H01L21/683 ,  H01L23/00 ,  H01L27/092 ,  H01L21/306 ,  H01L29/04 ,  H01L23/528 ,  H01L29/08 ,  H01L21/66 ,  H01L29/06 ,  H01L29/20 ,  H01L23/532 ,  H01L29/16 ,  G01R1/073 ,  H01L29/66 ,  H01L25/065

Abstract: Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Electrical test may be performed from front and back sides of a workpiece. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.