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    Characterizing and margining multi-voltage signal encoding for interconnects
    11.
    发明授权
    Characterizing and margining multi-voltage signal encoding for interconnects 有权

    公开(公告)号：US12155474B2

    公开(公告)日：2024-11-26

    申请号：US17086085

    申请日：2020-10-30

    Applicant: Intel Corporation

    Inventor： Debendra Das Sharma ,  Per E. Fornberg ,  Tal Israeli ,  Zuoguo Wu

    IPC: H04L1/00 ,  H03M13/00 ,  H03M13/09

    Abstract: Systems and apparatuses can include a receiver that includes port to receive a flow control unit (Flit) across a link, the link comprising a plurality of lanes. The receiver can also include error detection circuitry to determine an error in the Flit, an error counter to count a number of errors received, the error counter to increment based on an error detected in the Flit by the error detection circuitry, a Flit counter to count a number of Flits received, the Flit counter to increment based on receiving a Flit, and bit error rate logic to determine a bit error rate based on a count recorded by the error counter and a number of bits received as indicated by the Flit counter. The systems and apparatuses can apply processes to perform direct BER measurements at the receiver.

    STANDARD INTERFACES FOR DIE TO DIE (D2D) INTERCONNECT STACKS
    13.
    发明申请
    STANDARD INTERFACES FOR DIE TO DIE (D2D) INTERCONNECT STACKS 有权

    公开(公告)号：US20220327083A1

    公开(公告)日：2022-10-13

    申请号：US17844366

    申请日：2022-06-20

    Applicant: Intel Corporation

    Inventor： Debendra Das Sharma ,  Swadesh Choudhary ,  Narasimha Lanka ,  Zuoguo Wu ,  Gerald Pasdast ,  Lakshmipriya Seshan

    IPC: G06F13/42 ,  H01L23/538 ,  G06F13/40

    Abstract: In one embodiment, a first die comprises: a first die-to-die adapter to communicate with first protocol layer circuitry via a flit-aware die-to-die interface (FDI) and first physical layer circuitry via a raw die-to-die interface (RDI), where the first die-to-die adapter is to receive message information comprising first information of a first interconnect protocol; and the first physical layer circuitry coupled to the first die-to-die adapter. The first physical layer circuitry may be configured to receive and output the first information to a second die via an interconnect, the first physical layer circuitry comprising a plurality of modules, each of the plurality of modules comprising an analog front end having transmitter circuitry and receiver circuitry. Other embodiments are described and claimed.

    Integrated circuit package with test circuitry for testing a channel between dies
    14.
    发明授权
    Integrated circuit package with test circuitry for testing a channel between dies 有权

    公开(公告)号：US11450613B2

    公开(公告)日：2022-09-20

    申请号：US15933934

    申请日：2018-03-23

    Applicant: Intel Corporation

    Inventor： Mayue Xie ,  Jong-Ru Guo ,  Zhiguo Qian ,  Zuoguo Wu

    IPC: H01L23/538 ,  H01L25/065 ,  H01L23/58 ,  G01R31/28

    Abstract: Apparatuses, systems and methods associated with integrated circuit packages with integrated test circuitry for testing of a channel between dies are disclosed herein. In embodiments, an integrated circuit (IC) package may include a first die, a second die, and a channel that couples the first die to the second die. The first die may include a transmitter, test circuitry coupled between the transmitter and the channel, wherein the test circuitry is to control charge and discharge of the channel, and a receiver coupled to the channel. The receiver may determine a voltage of the channel during charge and discharge of the channel, and output an indication of the voltage. Other embodiments may be described and/or claimed.

    ALTERNATE PHYSICAL LAYER POWER MODE
    15.
    发明申请
    ALTERNATE PHYSICAL LAYER POWER MODE 有权

    公开(公告)号：US20220011849A1

    公开(公告)日：2022-01-13

    申请号：US17485371

    申请日：2021-09-25

    Applicant: Intel Corporation

    Inventor： Michelle C. Jen ,  David J. Harriman ,  Zuoguo Wu ,  Debendra Das Sharma ,  Noam Dolev Geldbard

    IPC: G06F1/3234 ,  G06F3/06 ,  G06F1/3225

    Abstract: A device includes physical layer (PHY) circuitry including a physical coding sublayer, where the PHY circuitry is configured to alternatively support at least two different power control settings. The device further includes an interface to couple the PHY circuitry to a media access control (MAC) layer, where the interface comprises a set of data pins, a set of command pins, a set of status pins, one or more clock pins, and a plurality of power control pins to receive an indication of a particular one of the at least two power control settings. The PHY circuitry is to apply parameters corresponding to the particular control setting during operation based on the indication.

    PHY-BASED RETRY TECHNIQUES FOR DIE-TO-DIE INTERFACES
    16.
    发明申请
    PHY-BASED RETRY TECHNIQUES FOR DIE-TO-DIE INTERFACES 有权

    公开(公告)号：US20210344354A1

    公开(公告)日：2021-11-04

    申请号：US17359517

    申请日：2021-06-26

    Applicant: Intel Corporation

    Inventor： Narasimha Lanka ,  Lakshmipriya Seshan ,  Debendra Das Sharma ,  Zuoguo Wu ,  Gerald S. Pasdast

    IPC: H03M13/11 ,  H03M13/00

    Abstract: In one embodiment, an apparatus includes PHY circuitry to implement a PHY-based retry technique, e.g., in die-to-die interfaces. The PHY circuitry includes a retry buffer to buffer data provided by the interface controller and error detection code generation circuitry to generate error detection codes based on input data. The PHY circuitry is to implement the retry technique by detecting a stall signal asserted by another apparatus across the channel, causing the error detection code generation circuitry to generate error detection codes based on data in the retry buffer, and transmitting the data from the retry buffer and its corresponding error detection codes across the channel to the other apparatus.

    Multichip package link error detection
    17.
    发明授权
    Multichip package link error detection 有权

    公开(公告)号：US11061761B2

    公开(公告)日：2021-07-13

    申请号：US16779391

    申请日：2020-01-31

    Applicant: Intel Corporation

    Inventor： Venkatraman Iyer ,  Robert G. Blankenship ,  Mahesh Wagh ,  Zuoguo Wu

    IPC: G06F11/10 ,  H03M13/00 ,  H04L29/06 ,  H04L1/00 ,  H04L1/20 ,  G06F13/16 ,  H04L1/16

    Abstract: First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.

    Characterization of transmission media
    18.
    发明授权
    Characterization of transmission media 有权

    公开(公告)号：US10908206B2

    公开(公告)日：2021-02-02

    申请号：US16302555

    申请日：2016-05-17

    Applicant: Intel Corporation

    Inventor： Mayue Xie ,  Chengqing Hu ,  Jong-Ru Guo ,  Zuoguo Wu ,  Deepak Goyal

    IPC: G01R31/28 ,  G01R31/11 ,  H04B10/071

    Abstract: Disclosed herein are systems and methods for the characterization of transmission media, among other embodiments. For example, a system for characterizing a transmission medium may include: a waveform generator to generate an initial input waveform; waveform pre-processing circuitry to process the initial waveform to generate a processed input waveform for provision to the transmission medium, wherein the processed input waveform has a maximum amplitude greater than a maximum amplitude of the initial input waveform; and waveform output circuitry to display or store data representative of an initial output waveform, wherein the initial output waveform is output from the transmission medium as a reflection or transmission of the processed input waveform.

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