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公开(公告)号：US09121100B2
公开(公告)日：2015-09-01
申请号：US13715477
申请日：2012-12-14
Applicant: Intermolecular Inc.
Inventor： Mohd Fadzli Anwar Hassan , Guowen Ding , Minh Huu Le , Minh Anh Anh Nguyen , Zhi-Wen Wen Sun , Guizhen Zhang
CPC classification number: H05K1/092 , C23C28/42 , C23C30/00 , H01L51/0097 , H01L51/5234 , H05K1/0274 , Y10T428/265
Abstract: Methods for making conducting stacks includes forming a doped or alloyed silver layer sandwiched between two layers of transparent conductive oxide such as indium tin oxide (ITO). The doped silver or silver alloy layer can be thin, such as between 1.5 to 20 nm and thus can be transparent. The doped silver or silver alloy can provide improved ductility property, allowing the conductive stack to be bendable. The transparent conductive oxide layers can also be thin, allowing the conductive stack to have an improved ductility property.
Abstract translation: 制造导电叠层的方法包括形成夹在两层透明导电氧化物（例如氧化铟锡（ITO））之间的掺杂或合金化的银层。 掺杂的银或银合金层可以是薄的，例如在1.5至20nm之间，因此可以是透明的。 掺杂的银或银合金可以提供改善的延展性，允许导电叠层可弯曲。 透明导电氧化物层也可以是薄的，允许导电叠层具有改善的延展性。
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12.发明申请SYSTEMS, METHODS, AND APPARATUS FOR PRODUCTION COATINGS OF LOW-EMISSIVITY GLASS 有权低功率玻璃生产涂料的系统，方法和装置公开(公告)号：US20140322507A1
公开(公告)日：2014-10-30
申请号：US14144915
申请日：2013-12-31
Applicant: Intermolecular Inc.
Inventor： Guowen Ding , Jeremy Cheng , Muhammad Imran , Minh Huu Le , Daniel Schweigert , Yongli Xu , Guizhen Zhang
CPC classification number: G02B5/208 , B29D11/00865 , C03C17/36 , C03C17/3626 , C03C17/3639 , C03C17/3644 , C03C17/366 , C03C17/3681 , C03C23/007 , C03C2217/43 , C03C2217/48 , C03C2218/154 , C23C14/083 , C23C14/085 , C23C14/14 , C23C14/22 , E06B9/24 , E06B2009/2417 , E06B2009/2464 , G02B5/26 , G02F1/091 , G02F2001/094 , Y10T428/24975 , Y10T428/265
Abstract: Disclosed herein are systems, methods, and apparatus for forming low emissivity panels. In some embodiments, a partially fabricated panel may be provided that includes a substrate, a reflective layer formed over the substrate, and a barrier layer formed over the reflective layer such that the reflective layer is formed between the substrate and the barrier layer. The barrier layer may include a partially oxidized alloy of three or more metals. A first interface layer may be formed over the barrier layer. A top dielectric layer may be formed over the first interface layer. The top dielectric layer may be formed using reactive sputtering in an oxygen containing environment. The first interface layer may prevent further oxidation of the partially oxidized alloy of the three or more metals when forming the top dielectric layer. A second interface layer may be formed over the top dielectric layer.
Abstract translation: 本文公开了用于形成低发射率面板的系统，方法和装置。 在一些实施例中，可以提供部分制造的面板，其包括衬底，在衬底上形成的反射层，以及形成在反射层上的阻挡层，使得反射层形成在衬底和阻挡层之间。 阻挡层可以包括三种或更多种金属的部分氧化的合金。 可以在阻挡层上方形成第一界面层。 可以在第一界面层上形成顶部电介质层。 可以在含氧环境中使用反应性溅射形成顶部电介质层。 当形成顶部电介质层时，第一界面层可以防止三种或更多种金属的部分氧化的合金的进一步氧化。 可以在顶部介电层上方形成第二界面层。
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公开(公告)号：US20140272353A1
公开(公告)日：2014-09-18
申请号：US13801465
申请日：2013-03-13
Applicant: INTERMOLECULAR INC.
Inventor： Guowen Ding , Jeremy Cheng , Tong Ju , Minh Huu Le , Daniel Schweigert , Guizhen Zhang
CPC classification number: G02B1/10 , C03C17/3615 , C03C17/3618 , C03C17/3626 , C03C17/3639 , C03C17/3644 , C03C17/3652 , C03C17/366 , C03C17/3681 , C03C2217/256 , G02B5/282 , G02B5/285 , Y10T428/24975 , Y10T428/265
Abstract: Low emissivity panels can include a protection layer of silicon nitride on a layer of ZnO on a layer of Zn2SnOx. The low emissivity panels can also include NiNbTiOx as a barrier layer. The low emissivity panels have high light to solar gain, color neutral, together with similar observable color and light transmission before and after a heat treatment process.
Abstract translation: 低发射率面板可以包括在Zn2SnOx层上的ZnO层上的氮化硅保护层。 低辐射面板还可以包括NiNbTiOx作为阻挡层。 低辐射面板在热处理过程之前和之后具有高的太阳光增益，颜色中性以及类似的可观察到的颜色和光透射。
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14.发明授权Barrier layers for silver reflective coatings and HPC workflows for rapid screening of materials for such barrier layers 有权用于银反射涂层的阻隔层和用于快速筛选这种阻挡层的材料的HPC工作流程公开(公告)号：US09127348B2
公开(公告)日：2015-09-08
申请号：US14574755
申请日：2014-12-18
Applicant: Intermolecular Inc.
Inventor： Guizhen Zhang , Jeremy Cheng , Guowen Ding , Minh Huu Le , Daniel Schweigert , Yu Wang
IPC: B32B15/04 , B32B17/06 , C23C14/08 , C23C14/22 , C03C17/36 , C23C14/14 , C23C14/00 , C23C14/04 , C23C14/34
CPC classification number: C23C14/22 , C03C17/36 , C03C17/3605 , C03C17/3618 , C03C17/3644 , C03C17/3652 , C03C17/366 , C03C17/3681 , C23C14/0036 , C23C14/042 , C23C14/14 , C23C14/34 , G02B1/12 , G02B1/14 , Y10T428/12542 , Y10T428/12549 , Y10T428/12611 , Y10T428/12778 , Y10T428/31678
Abstract: Provided is High Productivity Combinatorial (HPC) testing methodology of semiconductor substrates, each including multiple site isolated regions. The site isolated regions are used for testing different compositions and/or structures of barrier layers disposed over silver reflectors. The tested barrier layers may include all or at least two of nickel, chromium, titanium, and aluminum. In some embodiments, the barrier layers include oxygen. This combination allows using relative thin barrier layers (e.g., 5-30 Angstroms thick) that have high transparency yet provide sufficient protection to the silver reflector. The amount of nickel in a barrier layer may be 5-10% by weight, chromium—25-30%, titanium and aluminum—30%-35% each. The barrier layer may be co-sputtered in a reactive or inert-environment using one or more targets that include all four metals. An article may include multiple silver reflectors, each having its own barrier layer.
Abstract translation: 提供了半导体衬底的高生产率组合（HPC）测试方法，每个包括多个现场隔离区域。 位置隔离区域用于测试布置在银反射器上的阻挡层的不同组成和/或结构。 经测试的阻挡层可以包括镍，铬，钛和铝中的全部或至少两种。 在一些实施例中，阻挡层包括氧。 该组合允许使用具有高透明度的相对薄的阻挡层（例如5-30埃厚），同时为银反射器提供足够的保护。 阻挡层中的镍的量可以是5-10重量％，铬25-30％，钛和铝30％-35％。 阻挡层可以在反应性或惰性环境中使用包括所有四种金属的一种或多种目标共溅射。 物品可以包括多个银反射器，每个具有其自己的阻挡层。
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公开(公告)号：US20150191965A1
公开(公告)日：2015-07-09
申请号：US14662583
申请日：2015-03-19
Applicant: Intermolecular Inc.
Inventor： Guowen Ding , Brent Boyce , Tong Ju , Minh Huu Le , Phil Lingle , Daniel Schweigert , Yongli Xu , Guizhen Zhang
CPC classification number: E06B3/6715 , C03C17/36 , C03C17/3639 , C03C17/3644 , C03C17/366 , C03C17/3681 , Y10T428/24975 , Y10T428/265
Abstract: Embodiments provided herein describe low-e panels and methods for forming low-e panels. A transparent substrate is provided. A low-e stack is formed above the transparent substrate. Each of the layers of the low-e stack are formed to have a specific thickness to tune the performance characteristics of the low-e panel.
Abstract translation: 本文提供的实施例描述了用于形成低e板的低e板和方法。 提供透明基板。 在透明基板的上方形成低e堆叠。 低e叠层的每个层都形成为具有特定厚度以调节低e面板的性能特性。
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Patent Agency Ranking
16.发明申请公开(公告)号：US20140272395A1
公开(公告)日：2014-09-18
申请号：US14203182
申请日：2014-03-10
Applicant: Intermolecular Inc.
Inventor： Guowen Ding , Jeremy Cheng , Tong Ju , Minh Huu Le , Daniel Schweigert , Zhi-Wen Wen Sun , Yongli Xu , Guizhen Zhang
IPC: C03C17/36
CPC classification number: G02B5/208 , B29D11/00865 , C03C17/36 , C03C17/3626 , C03C17/3639 , C03C17/3644 , C03C17/366 , C03C17/3681 , C03C23/007 , C03C2217/43 , C03C2217/48 , C03C2218/154 , C23C14/083 , C23C14/085 , C23C14/14 , C23C14/22 , E06B9/24 , E06B2009/2417 , E06B2009/2464 , G02B5/26 , G02F1/091 , G02F2001/094 , Y10T428/24975 , Y10T428/265
Abstract: Disclosed herein are systems, methods, and apparatus for forming low emissivity panels that may include a first reflective layer, a second reflective layer, and a spacer layer disposed between the first reflective layer and the second reflective layer. In some embodiments, the spacer layer may have a thickness of between about 20 nm and 90 nm. The spacer layer may include a bi-metal oxide that may include tin, and may further include one of zinc, aluminum, or magnesium. The spacer layer may have a substantially amorphous structure. Moreover, the spacer layer may have a substantially uniform composition throughout the thickness of the spacer layer. The low emissivity panel may be configured to have a color change as determined by Rg ΔE (i.e. as determined on the glass side) that is less than about 1.7 in response to an application of a heat treatment to the low emissivity panel.
Abstract translation: 本文公开了用于形成低辐射率面板的系统，方法和装置，其可以包括设置在第一反射层和第二反射层之间的第一反射层，第二反射层和间隔层。 在一些实施例中，间隔层可以具有在约20nm和90nm之间的厚度。 间隔层可以包括可以包括锡的双金属氧化物，并且还可以包括锌，铝或镁中的一种。 间隔层可以具有基本上无定形的结构。 此外，间隔层可以在间隔层的整个厚度上具有基本均匀的组成。 低发射率面板可以被配置为响应于对低发射率面板的热处理的应用而具有小于约1.7的由Rg＆Dgr; E（即，在玻璃面上确定）确定的颜色变化。
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公开(公告)号：US20130122643A1
公开(公告)日：2013-05-16
申请号：US13738931
申请日：2013-01-10
Applicant: Intermolecular, Inc.
Inventor： Guowen Ding , Minh Huu Le , Guizhen Zhang
IPC: H01L31/032
CPC classification number: H01L31/0324 , C23C14/024 , C23C14/0641 , C23C14/5866 , H01L21/02422 , H01L21/02439 , H01L21/02485 , H01L21/02491 , H01L21/02502 , H01L21/02505 , H01L21/02521 , H01L21/02568 , H01L21/02631 , H01L31/032 , H01L31/072 , H01L31/0749 , Y02E10/541 , Y02P70/521
Abstract: Methods for forming Cu—In—Ga—N (CIGN) layers for use in TFPV solar panels are described using reactive PVD deposition in a nitrogen containing atmosphere. In some embodiments, the CIGN layers can be used as an absorber layer and eliminate the need of a selenization step. In some embodiments, the CIGN layers can be used as a protective layer to decrease the sensitivity of the CIG layer to oxygen or moisture before the selenization step. In some embodiments, the CIGN layers can be used as an adhesion layer to improve the adhesion between the back contact layer and the absorber layer.
Abstract translation: 在含氮气氛中使用反应性PVD沉积描述了用于TFPV太阳能电池板中形成Cu-In-Ga-N（CIGN）层的方法。 在一些实施方案中，CIGN层可以用作吸收层，并且不需要硒化步骤。 在一些实施方案中，CIGN层可用作保护层，以在硒化步骤之前降低CIG层对氧或水分的敏感性。 在一些实施方案中，CIGN层可以用作粘合层以改善背接触层和吸收层之间的粘附。
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公开(公告)号：US09410359B2
公开(公告)日：2016-08-09
申请号：US14662583
申请日：2015-03-19
Applicant: Intermolecular Inc.
Inventor： Guowen Ding , Brent Boyce , Tong Ju , Minh Huu Le , Phil Lingle , Daniel Schweigert , Yongli Xu , Guizhen Zhang
CPC classification number: E06B3/6715 , C03C17/36 , C03C17/3639 , C03C17/3644 , C03C17/366 , C03C17/3681 , Y10T428/24975 , Y10T428/265
Abstract: Embodiments provided herein describe low-e panels and methods for forming low-e panels. A transparent substrate is provided. A low-e stack is formed above the transparent substrate. Each of the layers of the low-e stack are formed to have a specific thickness to tune the performance characteristics of the low-e panel.
Abstract translation: 本文提供的实施例描述了用于形成低e板的低e板和方法。 提供透明基板。 在透明基板的上方形成低e堆叠。 低e叠层的每个层都形成为具有特定厚度以调节低e面板的性能特性。
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公开(公告)号：US09408303B2
公开(公告)日：2016-08-02
申请号：US14807336
申请日：2015-07-23
Applicant: Intermolecular Inc.
Inventor： Mohd Fadzli Anwar Hassan , Guowen Ding , Minh Huu Le , Minh Anh Nguyen , Zhi-Wen Sun , Guizhen Zhang
CPC classification number: H05K1/092 , C23C28/42 , C23C30/00 , H01L51/0097 , H01L51/5234 , H05K1/0274 , Y10T428/265
Abstract: Coated articles are disclosed. The coated articles include a doped or alloyed silver layer sandwiched between two layers of transparent conductive oxide such as indium tin oxide (ITO). The doped silver or silver alloy layer can be thin, such as between 1. 5 to 20 nm and thus can be transparent. The doped silver or silver alloy can provide improved ductility property, allowing the conductive stack to be bendable. The transparent conductive oxide layers can also be thin, allowing the conductive stack can have improved ductility property.
Abstract translation: 公开了涂层制品。 涂覆制品包括夹在两层透明导电氧化物如铟锡氧化物（ITO）之间的掺杂或合金化的银层。 掺杂的银或银合金层可以是薄的，例如在1.5至20nm之间，因此可以是透明的。 掺杂的银或银合金可以提供改善的延展性，允许导电叠层可弯曲。 透明导电氧化物层也可以是薄的，使得导电叠层可以具有改善的延展性。
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公开(公告)号：US20150327366A1
公开(公告)日：2015-11-12
申请号：US14807336
申请日：2015-07-23
Applicant: Intermolecular Inc.
Inventor： Mohd Fadzli Anwar Hassan , Guowen Ding , Minh Huu Le , Minh Anh Anh Nguyen , Zhi-Wen Wen Sun , Guizhen Zhang
CPC classification number: H05K1/092 , C23C28/42 , C23C30/00 , H01L51/0097 , H01L51/5234 , H05K1/0274 , Y10T428/265
Abstract: Methods for making conducting stacks includes forming a doped or alloyed silver layer sandwiched between two layers of transparent conductive oxide such as indium tin oxide (ITO). The doped silver or silver alloy layer can be thin, such as between 1.5 to 20 nm and thus can be transparent. The doped silver or silver alloy can provide improved ductility property, allowing the conductive stack to be bendable. The transparent conductive oxide layers can also be thin, allowing the conductive stack can have improved ductility property.
Abstract translation: 制造导电叠层的方法包括形成夹在两层透明导电氧化物（例如氧化铟锡（ITO））之间的掺杂或合金化的银层。 掺杂的银或银合金层可以是薄的，例如在1.5至20nm之间，因此可以是透明的。 掺杂的银或银合金可以提供改善的延展性，允许导电叠层可弯曲。 透明导电氧化物层也可以是薄的，使得导电叠层可以具有改善的延展性。
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