公开(公告)号：US08969189B2

公开(公告)日：2015-03-03

申请号：US14027315

申请日：2013-09-16

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-chen Yeh ,  Yunpeng Yin

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/28

CPC classification number: H01L21/28132 ,  H01L21/76801 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

Abstract: After formation of a replacement gate structure, a template dielectric layer employed to pattern the replacement gate structure is removed. After deposition of a dielectric liner, a first dielectric material layer is deposited by an anisotropic deposition and an isotropic etchback. A second dielectric material layer is deposited and planarized employing the first dielectric material portion as a stopping structure. The first dielectric material portion is removed selective to the second dielectric material layer, and is replaced with gate cap dielectric material portion including at least one dielectric material different from the materials of the dielectric material layers. A contact via hole extending to a source/drain region is formed employing the gate cap dielectric material portion as an etch stop structure. A contact via structure is spaced from the replacement gate structure at least by remaining portions of the gate cap dielectric material portion.

Abstract translation: 在形成替代栅极结构之后，去除用于对置换栅极结构进行图案化的模板电介质层。 在沉积介电衬垫之后，通过各向异性沉积和各向同性回蚀沉积第一介电材料层。 使用第一介电材料部分作为停止结构沉积和平坦化第二电介质材料层。 第一电介质材料部分被选择性地移除到第二电介质材料层，并且被包括不同于介电材料层的材料的至少一种介电材料的栅极盖电介质材料部分代替。 使用栅极绝缘材料部分作为蚀刻停止结构形成延伸到源极/漏极区域的接触孔。 接触通孔结构至少通过栅极盖电介质材料部分的剩余部分与替代栅极结构间隔开。

公开(公告)号：US20150054121A1

公开(公告)日：2015-02-26

申请号：US14035313

申请日：2013-09-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L29/06

CPC classification number: H01L29/0649 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: A method for semiconductor fabrication includes patterning one or more mandrels over a semiconductor substrate, the one or more mandrels having dielectric material formed therebetween. A semiconductor layer is formed over exposed portions of the one or more mandrels. A thermal oxidation is performed to diffuse elements from the semiconductor layer into an upper portion of the one or more mandrels and concurrently oxidize a lower portion of the one or more mandrels to form the one or more mandrels on the dielectric material.

Abstract translation: 一种用于半导体制造的方法包括在半导体衬底上图形化一个或多个心轴，所述一个或多个心轴在其间形成介电材料。 在一个或多个心轴的暴露部分上形成半导体层。 执行热氧化以将元件从半导体层扩散到一个或多个心轴的上部，并且同时氧化一个或多个心轴的下部以在电介质材料上形成一个或多个心轴。

公开(公告)号：US08872244B1

公开(公告)日：2014-10-28

申请号：US13865512

申请日：2013-04-18

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-chen Yeh ,  Yunpeng Yin

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L21/28132 ,  H01L21/76801 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

Abstract: After formation of a replacement gate structure, a template dielectric layer employed to pattern the replacement gate structure is removed. After deposition of a dielectric liner, a first dielectric material layer is deposited by an anisotropic deposition and an isotropic etchback. A second dielectric material layer is deposited and planarized employing the first dielectric material portion as a stopping structure. The first dielectric material portion is removed selective to the second dielectric material layer, and is replaced with gate cap dielectric material portion including at least one dielectric material different from the materials of the dielectric material layers. A contact via hole extending to a source/drain region is formed employing the gate cap dielectric material portion as an etch stop structure. A contact via structure is spaced from the replacement gate structure at least by remaining portions of the gate cap dielectric material portion.

Abstract translation: 在形成替代栅极结构之后，去除用于对置换栅极结构进行图案化的模板电介质层。 在沉积介电衬垫之后，通过各向异性沉积和各向同性回蚀沉积第一介电材料层。 使用第一介电材料部分作为停止结构沉积和平坦化第二电介质材料层。 第一电介质材料部分被选择性地移除到第二电介质材料层，并且被包括不同于介电材料层的材料的至少一种介电材料的栅极盖电介质材料部分代替。 使用栅极绝缘材料部分作为蚀刻停止结构形成延伸到源极/漏极区域的接触孔。 接触通孔结构至少通过栅极盖电介质材料部分的剩余部分与替代栅极结构间隔开。

公开(公告)号：US08871649B2

公开(公告)日：2014-10-28

申请号：US13834946

申请日：2013-03-15

Applicant: GLOBAL FOUNDRIES Inc. ,  Renesas Electronics Corporation ,  International Business Machines Corporation

Inventor： Linus Jang ,  Yoshinori Matsui ,  Chiahsun Tseng

IPC: H01L21/311 ,  H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/31144

Abstract: One illustrative method disclosed herein involves forming a layer of insulating material, forming a patterned layer of photoresist above the layer of insulating material, wherein the patterned layer of photoresist has an opening defined therein, forming an internal spacer within the opening in the patterned layer of photoresist, wherein the spacer defines a reduced-size opening, performing an etching process through the reduced-size opening on the layer of insulating material to define a trench/hole type feature in the layer of insulating material, and forming a conductive structure in the trench/hole type feature in the layer of insulating material.

Abstract translation: 本文公开的一种说明性方法包括形成绝缘材料层，在绝缘材料层之上形成图案化的光致抗蚀剂层，其中所述图案化的光致抗蚀剂层具有限定在其中的开口，在图案化层中的开口内形成内部间隔物 光致抗蚀剂，其中间隔物限定尺寸较小的开口，通过绝缘材料层上的尺寸减小的开口执行蚀刻工艺，以在绝缘材料层中限定沟槽/孔型特征，并在该层中形成导电结构 绝缘材料层中的沟槽/孔型特征。

公开(公告)号：US20190206864A1

公开(公告)日：2019-07-04

申请号：US16272844

申请日：2019-02-11

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Siva Kanakasabapathy ,  Yunpeng Yin ,  Chiahsun Tseng ,  Junli Wang

IPC: H01L27/088 ,  H01L21/265 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/66795

Abstract: A process for etching a bulk integrated circuit substrate to form features on the substrate, such as fins, having substantially vertical walls comprises forming an etch stop layer beneath the surface of the substrate by ion implantation, e.g., carbon, oxygen, or boron ions or combinations thereof, masking the surface with a patterned etching mask that defines the features by openings in the mask to produce a masked substrate and etching the masked substrate to a level of the etch stop layer to form the features. In silicon substrates, ion implantation takes place along a silicon crystalline lattice beneath the surface of the substrate. The etchant comprises a halogen material that etches undoped silicon faster than the implants-rich silicon layer. This produces a circuit where the fins do not taper away from the vertical where they meet the substrate, and corresponding products and articles of manufacture having these features.

公开(公告)号：US10170327B2

公开(公告)日：2019-01-01

申请号：US15613774

申请日：2017-06-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L21/00 ,  H01L21/308 ,  H01L29/66 ,  H01L21/033 ,  H01L21/3065 ,  H01L21/3213

Abstract: Methods and structures for fabricating fins for multigate devices are disclosed. In accordance with one method, a plurality of sidewalls are formed in or on a plurality of mandrels over a semiconductor substrate such that each of the mandrels includes a first sidewall composed of a first material and a second sidewall composed of a second material that is different from the first material. The first sidewall of a first mandrel of the plurality of mandrels is selectively removed. In addition, a pattern composed of remaining sidewalls of the plurality of sidewalls is transferred onto an underlying layer to form a hard mask in the underlying layer. Further, the fins are formed by employing the hard mask and etching semiconducting material in the substrate.

公开(公告)号：US09627263B1

公开(公告)日：2017-04-18

申请号：US14953461

申请日：2015-11-30

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Siva Kanakasabapathy ,  Yunpeng Yin ,  Chiahsun Tseng ,  Junli Wang

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/308 ,  H01L27/088 ,  H01L21/265 ,  H01L21/3065 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/26533 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L27/0886 ,  H01L29/785

Abstract: A process for etching a bulk integrated circuit substrate to form features on the substrate, such as fins, having substantially vertical walls comprises forming an etch stop layer beneath the surface of the substrate by ion implantation, e.g., carbon, oxygen, or boron ions or combinations thereof, masking the surface with a patterned etching mask that defines the features by openings in the mask to produce a masked substrate and etching the masked substrate to a level of the etch stop layer to form the features. In silicon substrates, ion implantation takes place along a silicon crystalline lattice beneath the surface of the substrate. The etchant comprises a halogen material that etches undoped silicon faster than the implants-rich silicon layer. This produces a circuit where the fins do not taper away from the vertical where they meet the substrate, and corresponding products and articles of manufacture having these features.

公开(公告)号：US20170033103A1

公开(公告)日：2017-02-02

申请号：US15292187

申请日：2016-10-13

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Chiahsun Tseng ,  Yunpeng Yin

IPC: H01L27/088 ,  H01L27/12 ,  H01L21/8234 ,  H01L29/165

CPC classification number: H01L27/0886 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76202 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656

Abstract: A semiconductor device, having a heterogeneous silicon stack, wherein the heterogeneous silicon stack comprises at least a base layer, a doped silicon layer, and an undoped silicon layer. The semiconductor device further includes a plurality of silicon fins atop a doped silicon oxide fin layer and an undoped silicon oxide fin layer, wherein the plurality of silicon fins have a uniform width along the height of the plurality of silicon fins, and wherein the plurality of silicon fins have a plurality of hard mask caps.

Abstract translation: 一种具有异质硅堆叠的半导体器件，其中所述异质硅堆叠至少包括基极层，掺杂硅层和未掺杂的硅层。 半导体器件还包括在掺杂的氧化硅鳍层和未掺杂的氧化硅鳍层上面的多个硅散热片，其中多个硅散热片沿着多个硅散热片的高度具有均匀的宽度，并且其中多个 硅散热片具有多个硬掩模盖。

公开(公告)号：US09552988B2

公开(公告)日：2017-01-24

申请号：US15131341

申请日：2016-04-18

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Chi-Chun Liu ,  Alexander Reznicek ,  Chiahsun Tseng ,  Tenko Yamashita

IPC: H01L21/302 ,  H01L21/033 ,  H01L21/027 ,  H01L29/06

CPC classification number: H01L21/0337 ,  H01L21/0271 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0338 ,  H01L29/0657

Abstract: A method for DSA fin patterning includes forming a BCP layer over a lithographic stack, the BCP layer having first and second blocks, the lithographic stack disposed over a hard mask and substrate, and the hard mask including first and second dielectric layers; removing the first block to define a fin pattern in the BCP layer with the second block; etching the fin pattern into the first dielectric layer; filling the fin pattern with a tone inversion material; etching back the tone inversion material that overfills the fin pattern; removing the first dielectric layer selectively to define an inverted fin pattern from the tone inversion material; etching the inverted fin pattern into the second dielectric layer of the hard mask; removing the tone inversion material; and transferring the inverted fin pattern of the second dielectric layer into the substrate to define fins.

Abstract translation: 一种用于DSA鳍图形化的方法包括在光刻叠层上形成BCP层，所述BCP层具有第一和第二块，所述光刻堆叠设置在硬掩模和衬底上，并且所述硬掩模包括第一和第二电介质层; 移除所述第一块以在所述BCP层中与所述第二块定义鳍图案; 将鳍状图案蚀刻到第一介电层中; 用色调反转材料填充鳍图案; 蚀刻过度填充鳍图案的色调反转材料; 从所述色调反转材料中选择性地去除所述第一介质层以限定反转的翅片图案; 将倒置的翅片图案蚀刻到硬掩模的第二介电层中; 去除色调反转材料; 并将第二介电层的倒置鳍状图案转印到基板中以限定翅片。

公开(公告)号：US20160379823A1

公开(公告)日：2016-12-29

申请号：US15131341

申请日：2016-04-18

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Chi-Chun Liu ,  Alexander Reznicek ,  Chiahsun Tseng ,  Tenko Yamashita

IPC: H01L21/033 ,  H01L29/06 ,  H01L21/027

CPC classification number: H01L21/0337 ,  H01L21/0271 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0338 ,  H01L29/0657

Abstract: A method for DSA fin patterning includes forming a BCP layer over a lithographic stack, the BCP layer having first and second blocks, the lithographic stack disposed over a hard mask and substrate, and the hard mask including first and second dielectric layers; removing the first block to define a fin pattern in the BCP layer with the second block; etching the fin pattern into the first dielectric layer; filling the fin pattern with a tone inversion material; etching back the tone inversion material that overfills the fin pattern; removing the first dielectric layer selectively to define an inverted fin pattern from the tone inversion material; etching the inverted fin pattern into the second dielectric layer of the hard mask; removing the tone inversion material; and transferring the inverted fin pattern of the second dielectric layer into the substrate to define fins.

Abstract translation: 一种用于DSA鳍图形化的方法包括在光刻叠层上形成BCP层，所述BCP层具有第一和第二块，所述光刻堆叠设置在硬掩模和衬底上，并且所述硬掩模包括第一和第二电介质层; 移除所述第一块以在所述BCP层中与所述第二块定义鳍图案; 将鳍状图案蚀刻到第一介电层中; 用色调反转材料填充翅片图案; 蚀刻过度填充鳍图案的色调反转材料; 从所述色调反转材料中选择性地去除所述第一介质层以限定反转的翅片图案; 将倒置的翅片图案蚀刻到硬掩模的第二介电层中; 去除色调反转材料; 并将第二介电层的倒置鳍状图案转印到基板中以限定翅片。