公开(公告)号：US10892404B1

公开(公告)日：2021-01-12

申请号：US16506459

申请日：2019-07-09

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Saba Zare ,  Michael Rizzolo ,  Theodorus E. Standaert ,  Daniel Charles Edelstein

IPC: H01L21/00 ,  H01L43/12 ,  H01L43/08 ,  G11C11/16 ,  H01L27/22 ,  H01L43/10

Abstract: A method of forming a semiconductor structure includes forming a dielectric layer surrounding contacts over a top surface and bevel edge of a substrate, forming a sacrificial buffer layer over the dielectric layer, removing portions of the sacrificial buffer layer formed over the dielectric layer on the top surface of the substrate, and patterning device structures including one or more metal layers over the contacts, wherein patterning the device structures removes portions of the metal layers formed over the top surface of the substrate leaving the metal layers on the bevel edge. The method also includes forming an encapsulation layer and performing a bevel dry etch to remove the encapsulation layer and the metal layers on the bevel edge. The bevel dry etch damages the sacrificial buffer layer on the bevel edge underneath the metal layers. The method further includes removing the damaged sacrificial buffer layer from the bevel edge.

公开(公告)号：US12272545B2

公开(公告)日：2025-04-08

申请号：US16824559

申请日：2020-03-19

Applicant: International Business Machines Corporation

Inventor： Devika Sil ,  Ashim Dutta ,  Yann Mignot ,  John Christopher Arnold ,  Daniel Charles Edelstein ,  Kedari Matam ,  Cornelius Brown Peethala

IPC: H01L21/3213 ,  H01L21/02 ,  H01L21/3065

Abstract: A novel bevel etch sequence for embedded metal contamination removal from BEOL wafers is provided. In one aspect, a method of processing a wafer includes: performing a bevel dry etch to break up layers of contaminants with embedded metals which, post back-end-of line metallization, are deposited on a bevel of the wafer, which forms a damaged layer on surfaces of the wafer, and then performing a sequence of wet etches, following the bevel dry etch, to render the bevel of the wafer substantially free of contaminants, wherein the sequence of wet etches includes etching the damaged layer to undercut and lift-off any remaining contaminants. A wafer, processed in this manner, having a bevel that is substantially free of contaminants is also provided.

公开(公告)号：US20250087527A1

公开(公告)日：2025-03-13

申请号：US18466783

申请日：2023-09-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Prabudhya Roy Chowdhury ,  Daniel Charles Edelstein ,  Shay Reboh

IPC: H01L21/74 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/528 ,  H01L23/535

Abstract: A semiconductor device includes a device wafer, including a silicon wafer. A handler wafer is bonded to the device wafer. The handler wafer includes a 111 crystallographic direction silicon substrate.

公开(公告)号：US20240419882A1

公开(公告)日：2024-12-19

申请号：US18333685

申请日：2023-06-13

Applicant: International Business Machines Corporation

Inventor： Xiaoming Yang ,  SOMNATH GHOSH ,  Huai Huang ,  Yann Mignot ,  Kai Zhao ,  Daniel Charles Edelstein

IPC: G06F30/39

Abstract: Embodiments of the invention are directed to a computer system having a processor communicatively coupled to a memory. The processor performs processor operations that include accessing an electronic file that includes an electronic integrated circuit (IC) design. The electronic file is operable to control a fabrication system to fabricate an IC according to the electronic IC design. The processor operations further includes applying a bulging predication analysis to the electronic IC design; and making one or more changes to the electronic IC design based at least in part on a result of the bulging prediction analysis.

公开(公告)号：US20240079446A1

公开(公告)日：2024-03-07

申请号：US17929324

申请日：2022-09-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Shogo Mochizuki ,  Daniel Charles Edelstein ,  Lawrence A. Clevenger ,  Brent A. Anderson ,  Kisik Choi ,  Chanro Park ,  Christian Lavoie ,  Cornelius Brown Peethala ,  SON NGUYEN

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/66439 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/78696

Abstract: Embodiments of the invention include a transistor comprising a gate region and an epitaxial region, the transistor comprising a frontside opposite a backside. A backside contact is coupled to the epitaxial region and separated from the gate region by a bottom dielectric isolation layer and a backside protective spacer

公开(公告)号：US20230187349A1

公开(公告)日：2023-06-15

申请号：US17551675

申请日：2021-12-15

Applicant: International Business Machines Corporation

Inventor： Chih-Chao Yang ,  Daniel Charles Edelstein ,  Theodorus E. Standaert ,  Jon Slaughter

IPC: H01L23/528 ,  H01L45/00 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L45/12 ,  H01L45/1608 ,  H01L21/76877

Abstract: A semiconductor device and formation thereof. The semiconductor device including: a first bottom interconnect formed within a first dielectric layer and located within a logic area of the semiconductor device; a second bottom interconnect formed within the first dielectric layer and located within a memory area of the semiconductor device; and a memory device formed on top of the second bottom interconnect located within the memory area of the semiconductor device, wherein: a first metal material used to form the first bottom interconnect located in the logic area is different than a second metal material used to form the second bottom interconnect located in the memory area.

公开(公告)号：US20240431025A1

公开(公告)日：2024-12-26

申请号：US18214159

申请日：2023-06-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takeshi Nogami ,  Daniel Charles Edelstein ,  Wei-Tsu Tseng ,  James J. Kelly ,  Donald Francis Canaperi

IPC: H05K1/11 ,  C23C14/08 ,  C23C14/34 ,  H05K1/09 ,  H05K3/42

Abstract: A single-damascene interconnect comprises a first conductor line and a second conductor line. The single-damascene interconnect also comprises a via connecting the first conductor line and second conductor line. The via is filled with a low resistivity metal conductor. The low resistivity metal conductor has high corrosion resistance. The metal conductor is not the same material as the first or second conductor lines.

公开(公告)号：US20240332181A1

公开(公告)日：2024-10-03

申请号：US18128020

申请日：2023-03-29

Applicant: International Business Machines Corporation

Inventor： Tsung-Sheng Kang ,  Tao Li ,  Ruilong Xie ,  Daniel Charles Edelstein

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/02

CPC classification number: H01L23/5286 ,  H01L23/5223 ,  H01L23/5228 ,  H01L27/0266 ,  H01L27/0292

Abstract: A semiconductor structure is provided that includes an inverter including a p-type field transistor and an n-type field effect transistor) having a shared gate structure and located on a frontside of the structure. The semiconductor structure further includes a passive device located on a backside of the structure and electrically connected to the shared gate structure of the inverter by a backside extension contact structure, and a backside power distribution network electrically connected to the passive device.

公开(公告)号：US20240290688A1

公开(公告)日：2024-08-29

申请号：US18175903

申请日：2023-02-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tsung-Sheng Kang ,  Tao Li ,  Ruilong Xie ,  Daniel Charles Edelstein

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/481 ,  H01L21/76841 ,  H01L23/5226 ,  H01L23/5283

Abstract: A semiconductor IC device includes a super via. The super via includes a lower skip via and an upper skip via. A connecting wire may be directly between or may separate the lower skip via and the upper skip via. The upper skip via may be adequately electrically isolated from a surrounding wire by an upper liner. The lower skip via may be adequately electrically isolated from a surrounding wire by a lower liner. The super via along with the connecting wire may connect a wire in the lowest wiring level with a wire in the highest wiring level. Because of the lower liner and/or the upper liner, the super via may be utilized for wiring and routing through a backside level of the semiconductor IC device (e.g., potential or signal routing) and be utilized as a heat transfer conduit through the backside of the semiconductor IC device.

公开(公告)号：US20240105605A1

公开(公告)日：2024-03-28

申请号：US17934913

申请日：2022-09-23

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Daniel Charles Edelstein ,  Rajiv Joshi ,  Ravikumar Ramachandran ,  Eric Miller

IPC: H01L23/528 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/5226

Abstract: A semiconductor structure includes a front-end-of-line level including a plurality of field effect transistors electrically connected to a back-end-of-line interconnect level. The back-end-of-line interconnect level is located on a first side of the front-end-of-line level. A backside power rail is embedded within a backside interlayer dielectric located on a second side of the front-end-of-line level opposing the first side of the front-end-of-line level. The backside power rail is electrically connected to at least one field effect transistor of the plurality of field effect transistors. At least one backside field effect transistor is formed on a first semiconductor layer disposed, at least in part, above a passive device region. A first side of the passive device region is in contact with the first semiconductor layer and a second side of the passive device region, opposing the first side, is in contact with the back-end-of-line interconnect level.