公开(公告)号：US20230275141A1

公开(公告)日：2023-08-31

申请号：US18314850

申请日：2023-05-10

Applicant: International Business Machines Corporation

Inventor： Tao Li ,  Indira Seshadri ,  Nelson Felix ,  Eric Miller

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/66666 ,  H01L29/0847 ,  H01L29/0653 ,  H01L27/092 ,  H01L21/823885 ,  H01L21/823814 ,  H01L29/7827

Abstract: A technique relates to a semiconductor device. A first epitaxial material is formed under a bottom surface of a set of fins, the first epitaxial material being under fin channel regions of the set of fins. A second epitaxial material is formed adjacent to the first epitaxial material and remote from the fin channel regions, a combination of the first epitaxial material and the second epitaxial material forming a bottom source or drain (source/drain) layer. A top source/drain layer is formed on an upper portion of the set of fins, gate material being disposed around the set of fins between the top source/drain layer and the bottom source/drain layer.

公开(公告)号：US11543751B2

公开(公告)日：2023-01-03

申请号：US16851034

申请日：2020-04-16

Applicant: International Business Machines Corporation

Inventor： Abraham Arceo de la Pena ,  Jennifer Church ,  Nelson Felix ,  Ekmini Anuja De Silva

IPC: G03F7/09 ,  G03F7/20 ,  H01L21/027 ,  H01L21/04 ,  H01L21/033 ,  H01L21/02

Abstract: An exemplary semiconductor fabrication stack includes underlying layers; an organic planarization layer atop the underlying layers; a metal oxide hardmask atop the organic planarization layer and doped with both carbon and nitrogen; and an organic photoresist directly atop the doped metal oxide hardmask. In one or more embodiments, the doped metal oxide hardmask exhibits a water contact angle of greater than 80°.

公开(公告)号：US11515431B2

公开(公告)日：2022-11-29

申请号：US16877574

申请日：2020-05-19

Applicant: International Business Machines Corporation

Inventor： Indira Seshadri ,  Ekmini Anuja De Silva ,  Jing Guo ,  Ruqiang Bao ,  Muthumanickam Sankarapandian ,  Nelson Felix

IPC: H01L29/786 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/10

Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least a first channel region and a second channel region. The first channel region and the second channel region each include metal gate structures surrounding a different nanosheet channel layer. The metal gate structures of the first and second channel regions are respectively separated from each other by an unfilled gap. The method includes forming a gap fill layer between and in contact with gate structures surrounding nanosheet channel layers in multiple channel regions. Then, after the gap fill layer has been formed for each nanosheet stack, a masking layer is formed over the gate structures and the gap fill layer in at least a first channel region. The gate structures and the gap fill layer in at least a second channel region remain exposed.

公开(公告)号：US11245027B2

公开(公告)日：2022-02-08

申请号：US16813787

申请日：2020-03-10

Applicant: International Business Machines Corporation

Inventor： Tao Li ,  Indira Seshadri ,  Nelson Felix ,  Eric Miller

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78

Abstract: A technique relates to a semiconductor device. A first epitaxial material is formed under a bottom surface of a set of fins, the first epitaxial material being under fin channel regions of the set of fins. A second epitaxial material is formed adjacent to the first epitaxial material and remote from the fin channel regions, a combination of the first epitaxial material and the second epitaxial material forming a bottom source or drain (source/drain) layer. A top source/drain layer is formed on an upper portion of the set of fins, gate material being disposed around the set of fins between the top source/drain layer and the bottom source/drain layer.

公开(公告)号：US11239077B2

公开(公告)日：2022-02-01

申请号：US16682494

申请日：2019-11-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chi-Chun Liu ,  Nelson Felix ,  Yann Mignot ,  Ekmini Anuja De Silva ,  John Arnold ,  Allen Gabor

IPC: H01L21/4763 ,  H01L21/033 ,  H01L21/321 ,  H01L21/768

Abstract: A method for fabricating a semiconductor device includes forming a plurality of mandrel cuts from a first set of mandrels of a base structure using lithography, surrounding the first set of mandrels and a second set of mandrels of the base structure with spacer material to form mandrel-spacer structures, forming a flowable material layer on exposed surfaces of the mandrel-spacer structures, and performing additional processing, including forming a plurality of dielectric trenches within the base structure based on patterns formed in the flowable material layer.

公开(公告)号：US20220013405A1

公开(公告)日：2022-01-13

申请号：US17484347

申请日：2021-09-24

Applicant: International Business Machines Corporation

Inventor： Nelson Felix ,  Ekmini Anuja De Silva ,  Luciana Meli Thompson ,  Yann Mignot

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/033 ,  H01L21/3105 ,  H01L21/311

Abstract: One or more embodiments described herein include systems, and/or methods that facilitate fabrication of a semiconductor device using a spacer lithography-etch process. According to an embodiment, a method can comprise performing a first lithography exposure and etch over a first layer of a semiconductor device, where the first lithography exposure and etch comprises forming one or more mandrels on a first region of a second layer by employing a first photoresist layer. The method can further comprise forming one or more spacers on a sidewall of the one or more mandrels and covering a second region of the second layer, where the second region is adjacent to the one or more mandrels. The method can further comprise forming a cut over a third region of the second layer and filling the third region with first material.

公开(公告)号：US20210398816A1

公开(公告)日：2021-12-23

申请号：US17467428

申请日：2021-09-06

Applicant: International Business Machines Corporation

Inventor： Nelson Felix ,  Ekmini Anuja De Silva ,  Praveen Joseph ,  Ashim Dutta

IPC: H01L21/308 ,  H01L21/033

Abstract: An initial semiconductor structure includes an underlying substrate, a hard mask stack, an organic planarization layer (OPL), a first complementary material, and a patterned photoresist layer patterned into a plurality of photoresist pillars defining a plurality of photoresist trenches. The first material is partially etched inward of the trenches, to provide trench regions, and the photoresist is removed. The trench regions are filled with a second complementary material, preferentially etchable with respect to the first material. A polymer brush is grafted on the second material but not the first material, to form polymer brush regions with intermediate regions not covered by the brush. The first material is anisotropically etched the at the intermediate regions but not the brush regions. The OPL is etched inward of the intermediate regions, to provide a plurality of OPL pillars defining a plurality of OPL trenches inverted with respect to the photoresist pillars.

公开(公告)号：US11192101B2

公开(公告)日：2021-12-07

申请号：US16419684

申请日：2019-05-22

Applicant: International Business Machines Corporation

Inventor： Chi-Chun Liu ,  Yann Mignot ,  Joshua T. Smith ,  Bassem M. Hamieh ,  Nelson Felix ,  Robert L. Bruce

IPC: B01L3/00 ,  B81C1/00 ,  B81B7/00

Abstract: A microfluidic chip with high volumetric flow rate is provided that includes at least two vertically stacked microfluidic channel layers, each microfluidic channel layer including an array of spaced apart pillars. Each microfluidic channel layer is interconnected by an inlet/outlet opening that extends through the microfluidic chip. The microfluidic chip is created without wafer to wafer bonding thus circumventing the cost and yield issues associated with microfluidic chips that are created by wafer bonding.

公开(公告)号：US11131919B2

公开(公告)日：2021-09-28

申请号：US16015994

申请日：2018-06-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Yongan Xu ,  Zhenxing Bi ,  Yann Mignot ,  Nelson Felix ,  Ekmini A. De Silva

IPC: G03F7/11 ,  G03F7/42 ,  G03F7/20 ,  G03F7/36 ,  G03F7/09 ,  G03F1/22

Abstract: A method of removing layers of an extreme ultraviolet (EUV) pattern stack is provided. The method includes forming one or more resist templates on an upper hardmask layer. The method further includes exposing portions of the surface of the upper hardmask layer to a dry etch process to produce modified and activated surfaces. The method further includes etching the modified and activated surfaces to expose an underlying organic planarization layer.

公开(公告)号：US10741454B2

公开(公告)日：2020-08-11

申请号：US16059319

申请日：2018-08-09

Applicant: International Business Machines Corporation

Inventor： Jing Guo ,  Ekmini A. De Silva ,  Nicolas Loubet ,  Indira Seshadri ,  Nelson Felix

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L21/768 ,  H01L27/108

Abstract: Methods are presented for forming multi-threshold field effect transistors. The methods generally include depositing and patterning an organic planarizing layer to protect underlying structures formed in a selected one of the nFET region and the pFET region of a semiconductor wafer. In the other one of the nFET region and the pFET region, structures are processed to form an undercut in the organic planarizing layer. The organic planarizing layer is subjected to a reflow process to fill the undercut. The methods are effective to protect a boundary between the nFET region and the pFET region.