公开(公告)号：US20210408233A1

公开(公告)日：2021-12-30

申请号：US16916736

申请日：2020-06-30

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Reinaldo Vega ,  Kangguo Cheng ,  Chanro Park ,  Juntao Li

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L21/8234

Abstract: Embodiments of the invention are directed to a method of performing fabrication operations to form a transistor, wherein the fabrication operations include forming a source or drain (S/D) region having stacked, spaced-apart, and doped S/D layers. The fabrication operations further include forming a multi-region S/D contact structure configured to contact a top surface, a bottom surface, and sidewalls of each of the stacked, spaced-apart, and doped S/D layers.

公开(公告)号：US11211429B2

公开(公告)日：2021-12-28

申请号：US16285318

申请日：2019-02-26

Applicant: International Business Machines Corporation

Inventor： Jianshi Tang ,  Takashi Ando ,  Reinaldo Vega

IPC: H01L47/00 ,  H01L27/24 ,  H01L45/00

Abstract: Vertically stacked memory devices and methods of manufacture are provided. The structures include a substrate stack including a first row of horizontal electrodes disposed over a first insulating layer and first insulating layer disposed over a substrate. The substrate stack further includes a second row of horizontal electrodes separated from the first row of horizontal electrodes by a second insulating layer, and the first row of horizontal electrodes is form over and substantially parallel to the second row of horizontal electrodes. A third insulating layer is formed over the second row of horizontal electrodes. A plurality of vertical gate trenches formed through the third insulating layer, the second row of horizontal electrodes, the second insulating layer, the first row of horizontal electrodes and the first insulating layer. The plurality of vertical gate trenches filled with a layer of channel material, a layer of electrolyte material and filled with a metal.

公开(公告)号：US11177436B2

公开(公告)日：2021-11-16

申请号：US16394305

申请日：2019-04-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Praneet Adusumilli ,  Jianshi Tang ,  Reinaldo Vega

IPC: H01L45/00 ,  H01L27/24

Abstract: A method is presented for enabling heat dissipation in resistive random access memory (RRAM) devices. The method includes forming a first thermal conducting layer over a bottom electrode, depositing a metal oxide liner over the first thermal conducting layer, forming a second thermal conducting layer over the metal oxide liner, recessing the second thermal conducting layer to expose the first thermal conducting layer, and forming a top electrode in direct contact with the first and second thermal conducting layers.

公开(公告)号：US20210327762A1

公开(公告)日：2021-10-21

申请号：US16854276

申请日：2020-04-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Reinaldo Vega ,  Alexander Reznicek ,  Kangguo Cheng

IPC: H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L29/06 ,  H01L29/10 ,  H01L27/088

Abstract: A method for fabricating a semiconductor device includes forming a shared source/drain connection at a first planar level to connect a first source/drain contact structure disposed on a first source/drain region to a second source/drain contact structure disposed on a second source/drain region, and forming a shared gate connection to connect a first gate structure to a second gate structure. The shared gate connection is formed at a second planar level different from the first planar level to reduce parasitic capacitance between the shared source/drain connection and the shared gate connection.

公开(公告)号：US11119148B2

公开(公告)日：2021-09-14

申请号：US16164130

申请日：2018-10-18

Applicant: International Business Machines Corporation

Inventor： Pablo Nieves ,  Kushagra Sinha ,  Reinaldo Vega

IPC: G01R31/28 ,  G01R31/311 ,  G01R1/04 ,  G01R1/067 ,  H01L21/68

Abstract: A test probe assembly includes a probe card, a plurality of test probes mounted to the probe card with each of the test probes having a probe tip segment and a probe end for positioning adjacent respective individual test pads of a semiconductor wafer, and a fiber optic lead mounted to each test probe. The fiber optic leads are arranged to direct incident light toward respective individual test pads of the semiconductor wafer. A plurality of photodetectors may be arranged about the probe card with individual photodetectors configured for reception of light reflected off the respective individual test pads to emit output signals used to generate image data representative of the individual test pads on the semiconductor wafer. The image data may be utilized to align the test pads with the test probes for subsequent testing.

公开(公告)号：US20200373354A1

公开(公告)日：2020-11-26

申请号：US16422344

申请日：2019-05-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jianshi Tang ,  Takashi Ando ,  Reinaldo Vega ,  Praneet Adusumilli

IPC: H01L27/24 ,  H01L45/00 ,  G06N3/04

Abstract: A semiconductor device with an array of vertically stacked electrochemical random-access memory (ECRAM) devices, includes holes formed in a vertical stack of horizontal electrodes. The horizontal electrodes are horizontally aligned and stacked vertically at different vertical levels within the vertical stack and separated by first fill layers. The semiconductor device includes a stack deposition, including a channel layer, and an electrolyte layer, formed over the vertical stack and holes. Selector layers fill holes. The selector layers include an inner selector layer and outer selector layers. The channel layer, the electrolyte layer and outer selector layers are recessed to the inner selector layer and a fill layer is deposited over the vertical stack. The fill layer has been reduced down to the top of the inner selector layer.

公开(公告)号：US20200168706A1

公开(公告)日：2020-05-28

申请号：US16775726

申请日：2020-01-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Choonghyun Lee ,  Reinaldo Vega ,  Jingyun Zhang ,  Miaomiao Wang

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L21/28 ,  H01L29/49

Abstract: A method is presented for reducing external resistance of a vertical field-effect-transistor (FET). The method includes forming a plurality of fins over a sacrificial layer disposed over a substrate, selectively removing the sacrificial layer to form an etch stop layer in direct contact with the substrate, disposing embedded bottom source/drain regions between a bottom portion of the plurality of fins and the etch stop layer, disposing encapsulation layers over the plurality of fins, recessing at least one of the encapsulation layers to expose top portions of the plurality of fins, forming top spacers adjacent the top portions of the plurality of fins, and forming top source/drain regions over the top portions of the plurality of fins.

公开(公告)号：US20200083088A1

公开(公告)日：2020-03-12

申请号：US16126521

申请日：2018-09-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Huimei Zhou ,  Gen Tsutsui ,  Andrew M. Greene ,  Dechao Guo ,  Huiming Bu ,  Robert Robison ,  Veeraraghavan S. Basker ,  Reinaldo Vega

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L21/32

Abstract: Integrated chips and methods of forming the same include oxidizing a portion of a semiconductor fin to electrically isolate active regions of the semiconductor fin. A semiconductor device is formed on each of the active regions.

公开(公告)号：US10586854B2

公开(公告)日：2020-03-10

申请号：US15975869

申请日：2018-05-10

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Michael A. Guillorn ,  Terence Hook ,  Robert R. Robison ,  Reinaldo Vega ,  Tenko Yamashita

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/06 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/786

Abstract: One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.

公开(公告)号：US20200075723A1

公开(公告)日：2020-03-05

申请号：US16116012

申请日：2018-08-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Choonghyun Lee ,  Reinaldo Vega ,  Jingyun Zhang ,  Miaomiao Wang

IPC: H01L29/08 ,  H01L29/66 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

Abstract: A method is presented for reducing external resistance of a vertical field-effect-transistor (FET). The method includes forming a plurality of fins over a sacrificial layer disposed over a substrate, selectively removing the sacrificial layer to form an etch stop layer in direct contact with the substrate, disposing embedded bottom source/drain regions between a bottom portion of the plurality of fins and the etch stop layer, disposing encapsulation layers over the plurality of fins, recessing at least one of the encapsulation layers to expose top portions of the plurality of fins, forming top spacers adjacent the top portions of the plurality of fins, and forming top source/drain regions over the top portions of the plurality of fins.