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公开(公告)号：US09171742B2
公开(公告)日：2015-10-27
申请号：US13947543
申请日：2013-07-22
发明人： Evan G. Colgan , Steven A. Cordes , Daniel C. Edelstein , Vijayeshwar D. Khanna , Kenneth Latzko , Qinghuang Lin , Peter J. Sorce , Sri M. Sri-Jayantha , Robert L. Wisnieff , Roy R. Yu
IPC分类号： H01L21/00 , H01L21/50 , H01L25/00 , H01L25/065 , H01L29/06 , H01L23/02 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/50 , H01L25/0657 , H01L25/50 , H01L29/0657 , H01L2225/06513 , H01L2225/06593 , H01L2924/0002 , H01L2924/10156 , H01L2924/00
摘要： The present disclosure relates to methods and devices for manufacturing a three-dimensional chip package. A method includes forming a linear groove on an alignment rail, attaching an alignment rod to the linear groove, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail. Another method includes forming an alignment ridge on an alignment rail, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail.
摘要翻译： 本公开涉及用于制造三维芯片封装的方法和装置。 一种方法包括在对准导轨上形成直线槽，将对准杆连接到线性槽，在多个集成电路芯片上形成对准通道，并通过将多个集成电路芯片沿着 对准导轨 另一种方法包括在对准导轨上形成对准脊，在多个集成电路芯片上形成对准通道，并且通过沿对准导轨堆叠多个集成电路芯片来对准多个集成电路芯片。
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公开(公告)号：US20130224959A1
公开(公告)日：2013-08-29
申请号：US13772511
申请日：2013-02-21
IPC分类号： H01L21/306
CPC分类号： H01L21/306 , H01L21/32135 , H01L21/7684 , H01L21/76843 , H01L21/76849 , H01L21/76865 , H01L23/5227 , H01L23/53238 , H01L24/11 , H01L2224/13099 , H01L2924/01002 , H01L2924/01006 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01054 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/04953 , H01L2924/14 , H01L2924/19042 , H01L2924/30105 , H01L2924/00
摘要： Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.
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公开(公告)号：US11055459B2
公开(公告)日：2021-07-06
申请号：US16433675
申请日：2019-06-06
发明人： Qianwen Chen , Li-Wen Hung , Wanki Kim , John U. Knickerbocker , Kenneth P. Rodbell , Robert L. Wisnieff
IPC分类号： H01L25/065 , H01L25/07 , G06F30/331 , H01L23/31 , H01L25/00 , H01L23/00 , H01L21/683 , H01L25/11 , H01L21/56 , H01L25/18 , G06F15/78 , G06F15/80
摘要： A method of forming an electrical device is provided that includes forming microprocessor devices on a microprocessor die; forming memory devices on an memory device die; forming component devices on a component die; and forming a plurality of packing devices on a packaging die. Transferring a plurality of each of said microprocessor devices, memory devices, component devices and packaging components to a supporting substrate, wherein the packaging components electrically interconnect the memory devices, component devices and microprocessor devices in individualized groups. Sectioning the supporting substrate to provide said individualized groups of memory devices, component devices and microprocessor devices that are interconnected by a packaging component.
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公开(公告)号：US10592626B1
公开(公告)日：2020-03-17
申请号：US16155489
申请日：2018-10-09
摘要： Techniques and a system for visualization or interaction with a quantum processor are provided. In one example, a system includes a quantum programming component and a visualization component. The quantum programming component manages a quantum programming process to generate topology data for a quantum processor that is indicative of a physical topology of a set of qubits associated with the quantum processor. The visualization component generates visualization data for the topology data that comprises a set of planar slice elements arranged to correspond to the physical topology of the set of qubits. The set of planar slice elements indicate one or more operations performed at a time step associated with the quantum programming process.
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公开(公告)号：US10380284B2
公开(公告)日：2019-08-13
申请号：US15626582
申请日：2017-06-19
发明人： Qianwen Chen , Li-Wen Hung , Wanki Kim , John U. Knickerbocker , Kenneth P. Rodbell , Robert L. Wisnieff
IPC分类号： G06F17/50 , G06F15/78 , H01L25/00 , H01L23/31 , H01L23/00 , H01L21/683 , H01L25/065 , H01L25/11 , H01L25/07 , H01L21/56 , H01L25/18 , G06F15/80
摘要： A method of forming an electrical device is provided that includes forming microprocessor devices on a microprocessor die; forming memory devices on an memory device die; forming component devices on a component die; and forming a plurality of packing devices on a packaging die. Transferring a plurality of each of said microprocessor devices, memory devices, component devices and packaging components to a supporting substrate, wherein the packaging components electrically interconnect the memory devices, component devices and microprocessor devices in individualized groups. Sectioning the supporting substrate to provide said individualized groups of memory devices, component devices and microprocessor devices that are interconnected by a packaging component.
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公开(公告)号：US20170193775A1
公开(公告)日：2017-07-06
申请号：US15466122
申请日：2017-03-22
IPC分类号： G08B13/24 , H01L21/78 , H01L23/66 , H01L31/054 , H01L23/544
CPC分类号： G08B13/244 , G06K19/0704 , G06K19/0707 , G06K19/0716 , G06K19/0717 , G06K19/0723 , G06K19/07749 , G06K19/0775 , G06K19/07775 , H01L21/78 , H01L23/544 , H01L23/66 , H01L31/0547 , H01L2223/54426 , H01L2223/6677
摘要： A smart tag comprises a processor, a non-volatile memory, at least one of an internal power source and an external power source, and a transceiver configured for two-way communication with a reader external to the smart tag. The smart tag is formed as an integrated circuit chip less than 10 cubic millimeters in size to less than 0.000125 cubic millimeters in size. An apparatus comprising the smart tag may further include an antenna connect to the smart tag.
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公开(公告)号：US09684862B2
公开(公告)日：2017-06-20
申请号：US14927013
申请日：2015-10-29
IPC分类号： G06K19/077
CPC分类号： G08B13/244 , G06K19/0704 , G06K19/0707 , G06K19/0716 , G06K19/0717 , G06K19/0723 , G06K19/07749 , G06K19/0775 , G06K19/07775 , H01L21/78 , H01L23/544 , H01L23/66 , H01L31/0547 , H01L2223/54426 , H01L2223/6677
摘要： A smart tag comprises a processor, a non-volatile memory, at least one of an internal power source and an external power source, and a transceiver configured for two-way communication with a reader external to the smart tag. The smart tag is formed as an integrated circuit chip less than 10 cubic millimeters in size to less than 0.000125 cubic millimeters in size. An apparatus comprising the smart tag may further include an antenna connect to the smart tag.
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公开(公告)号：US20150024549A1
公开(公告)日：2015-01-22
申请号：US13947543
申请日：2013-07-22
发明人： Evan G. Colgan , Steven A. Cordes , Daniel C. Edelstein , Vijayeshwar D. Khanna , Kenneth Latzko , Qinghuang Lin , Peter J. Sorce , Sri M. Sri-Jayantha , Robert L. Wisnieff , Roy R. Yu
IPC分类号： H01L21/50
CPC分类号： H01L21/50 , H01L25/0657 , H01L25/50 , H01L29/0657 , H01L2225/06513 , H01L2225/06593 , H01L2924/0002 , H01L2924/10156 , H01L2924/00
摘要： The present disclosure relates to methods and devices for manufacturing a three-dimensional chip package. A method includes forming a linear groove on an alignment rail, attaching an alignment rod to the linear groove, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail. Another method includes forming an alignment ridge on an alignment rail, forming alignment channels on a plurality of integrated circuit chips, and aligning the plurality of integrated circuit chips by stacking the plurality of integrated circuit chips along the alignment rail.
摘要翻译： 本公开涉及用于制造三维芯片封装的方法和装置。 一种方法包括在对准导轨上形成直线槽，将对准杆连接到线性槽，在多个集成电路芯片上形成对准通道，并通过将多个集成电路芯片沿着 对准导轨 另一种方法包括在对准导轨上形成对准脊，在多个集成电路芯片上形成对准通道，并且通过沿对准导轨堆叠多个集成电路芯片来对准多个集成电路芯片。
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19.发明授权公开(公告)号：US08816717B2
公开(公告)日：2014-08-26
申请号：US13653996
申请日：2012-10-17
IPC分类号： H03K19/00
CPC分类号： H01L27/2472 , H01L23/576 , H01L27/24 , H01L45/06 , H01L45/1233 , H01L45/142 , H01L45/144 , H01L2924/0002 , Y10T29/49155 , H01L2924/00
摘要： The present disclosure relates to integrated circuits having tamper detection and response devices and methods for manufacturing such integrated circuits. One integrated circuit having a tamper detection and response device includes at least one reactive material and at least one memory cell coupled to the at least one reactive material. An exothermic reaction in the at least one reactive material causes an alteration to a memory state of the at least one memory cell. Another integrated circuit having a tamper detection and response device includes a substrate, at least one gate on the substrate, and a reactive material between a first well and a second well of the at least one gate. A reaction in the reactive material causes a short in the gate.
摘要翻译： 本公开涉及具有篡改检测和响应装置的集成电路以及用于制造这种集成电路的方法。 具有篡改检测和响应装置的一个集成电路包括至少一个反应性材料和至少一个耦合到所述至少一个反应性材料的存储单元。 所述至少一种反应性材料中的放热反应导致所述至少一个存储器单元的存储状态的改变。 具有篡改检测和响应装置的另一集成电路包括衬底，衬底上的至少一个栅极以及至少一个栅极的第一阱和第二阱之间的反应性材料。 反应性物质中的反应在浇口中引起短路。
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公开(公告)号：US20140175635A1
公开(公告)日：2014-06-26
申请号：US13721991
申请日：2012-12-20
IPC分类号： H01L23/538
CPC分类号： H01L23/5386 , H01L23/473 , H01L23/5384 , H01L23/5385 , H01L24/00 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2224/16145 , H01L2224/16225 , H01L2224/291 , H01L2224/2929 , H01L2224/293 , H01L2224/29339 , H01L2224/32145 , H01L2224/73253 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06558 , H01L2225/06562 , H01L2225/06572 , H01L2225/06589 , H01L2924/1434 , H01L2924/15311 , H01L2924/3511 , H01L2924/37001 , H01L2924/014
摘要： A packaging structure is provided. The packaging structure includes first and second chips, at least one surface of each of the first and second chips being an active surface and a common chip to which at least one of the first and second chips is electrically interconnected. The respective active surfaces of the first and second chips are directly electrically interconnected to one another in a face-to-face arrangement and are oriented transversely with respect to the common chip.
摘要翻译： 提供了一种包装结构。 封装结构包括第一和第二芯片，第一和第二芯片中的每一个的至少一个表面是有源表面，以及公共芯片，第一芯片和第二芯片中的至少一个芯片电连接到该芯片。 第一和第二芯片的各自的有效表面以面对面的布置彼此直接电互连，并相对于公共芯片横向取向。
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