公开(公告)号：US11456219B2

公开(公告)日：2022-09-27

申请号：US16849156

申请日：2020-04-15

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Dechao Guo ,  Junli Wang ,  Heng Wu

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/3215 ,  H01L21/28 ,  H01L29/78 ,  H01L29/06

Abstract: A technique relates to a semiconductor device. An N-type field effect transistor (NFET) and a P-type field effect transistor (PFET) each include an inner work function metal, an outer work function metal, a first nanosheet including an inner channel surface having a first threshold voltage, and a second nanosheet including an outer channel surface having a second threshold voltage. The outer work function metal is modified so as to cause the outer channel surface for the second nanosheet to have the second threshold voltage within a predefined amount of the first threshold voltage for the inner channel surface of the first nanosheet, the predefined amount being within about 20 millivolts (mV).

公开(公告)号：US20220238682A1

公开(公告)日：2022-07-28

申请号：US17718989

申请日：2022-04-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Huiming Bu

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/28 ,  H01L29/06 ,  H01L29/66

Abstract: A method for fabricating a semiconductor device includes forming an interfacial layer and a dielectric layer on a base structure and around channels of a first gate-all-around field-effect transistor (GAA FET) device within a first region and a second GAA FET device within a second region, forming at least a scavenging metal layer in the first and second regions, and performing an anneal process after forming at least one cap layer.

公开(公告)号：US11251285B2

公开(公告)日：2022-02-15

申请号：US16553912

申请日：2019-08-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Hemanth Jagannathan ,  Paul C. Jamison ,  ChoongHyun Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L21/324 ,  H01L21/02 ,  H01L29/49

Abstract: A method of forming a vertical fin field effect transistor device, including, forming one or more vertical fins with a hardmask cap on each vertical fin on a substrate, forming a fin liner on the one or more vertical fins and hardmask caps, forming a sacrificial liner on the fin liner, and forming a bottom spacer layer on the sacrificial liner.

公开(公告)号：US11245020B2

公开(公告)日：2022-02-08

申请号：US16745100

申请日：2020-01-16

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Michael A. Guillorn ,  Terence Hook ,  Robert R. Robison ,  Reinaldo Vega ,  Tenko Yamashita

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/06 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/786

Abstract: One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.

公开(公告)号：US20220013521A1

公开(公告)日：2022-01-13

申请号：US16946856

申请日：2020-07-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chen Zhang ,  Dechao Guo ,  Junli Wang ,  Ruilong Xie ,  Kangguo Cheng ,  Juntao Li ,  Chanro Park ,  Ruqiang Bao ,  Sung Dae Suk ,  Lan Yu ,  Heng Wu

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: An embodiment of the invention may include a semiconductor structure and method of manufacturing. The semiconductor structure may include a top channel and a bottom channel, wherein the top channel includes a plurality of vertically oriented channels. The bottom channel includes a plurality of horizontally oriented channels. The semiconductor structure may include a gate surrounding the top channel and the bottom channel. The semiconductor structure may include spacers located on each side of the gate. A first spacer includes a dielectric material located between the plurality of vertically oriented channels. A second spacer includes a dielectric material located between the plurality of horizontally oriented channels. This may enable spacer formation between the vertical spacers.

公开(公告)号：US20220005807A1

公开(公告)日：2022-01-06

申请号：US17481497

申请日：2021-09-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Koji Watanabe

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06

Abstract: A device is provided. The device includes an interfacial layer on a semiconductor device channel. The device further includes a dipole layer on the interfacial layer, and a gate dielectric layer on the dipole layer. The device further includes a first work function layer associated with a first field effect transistor device; and a second work function layer associated with a second field effect transistor device, such that the first field effect transistor device and second field effect transistor device each have a different threshold voltage than a first field effect transistor device and second field effect transistor device without a dipole layer.

公开(公告)号：US11152489B2

公开(公告)日：2021-10-19

申请号：US16681038

申请日：2019-11-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Kisup Chung ,  Andrew M. Greene ,  Sivananda K. Kanakasabapathy ,  David L. Rath ,  Indira P. V. Seshadri ,  Rajasekhar Venigalla

IPC: H01L29/66 ,  H01L21/768 ,  H01L23/535 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L21/8234 ,  H01L27/088

Abstract: An additive core subtractive liner method is described for forming electrically conductive contacts. The method can include forming a first trench in a first dielectric layer to expose a first portion of a metal liner, and filling said first trench with a second dielectric layer. A metal cut trench is formed in the second dielectric layer. A portion of the metal liner exposed by the metal cut trench is removed with a subtractive method. The method continues with filling the metal cut trench with a dielectric fill, and replacing the remaining portions of the second dielectric layer with an additive core conductor to provide contacts to remaining portions of the metal liner.

公开(公告)号：US10957646B2

公开(公告)日：2021-03-23

申请号：US16782311

申请日：2020-02-05

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Cornelius Brown Peethala ,  Michael Rizzolo ,  Koichi Motoyama ,  Gen Tsutsui ,  Ruqiang Bao ,  Gangadhara Raja Muthinti ,  Lawrence A. Clevenger

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/48 ,  H01L21/768 ,  H01L21/306

Abstract: A semiconductor wafer has a top surface, a dielectric insulator, a plurality of narrow copper wires, a plurality of wide copper wires, an optical pass through layer over the top surface, and a self-aligned pattern in a photo-resist layer. The plurality of wide copper wires and the plurality of narrow copper wires are embedded in a dielectric insulator. The width of each wide copper wire is greater than the width of each narrow copper. An optical pass through layer is located over the top surface. A self-aligned pattern in a photo-resist layer, wherein photo-resist exists only in areas above the wide copper wires, is located above the optical pass through layer.

公开(公告)号：US10832975B2

公开(公告)日：2020-11-10

申请号：US16006187

申请日：2018-06-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruqiang Bao ,  Brent A. Anderson ,  Junli Wang ,  Kangguo Cheng ,  Choonghyun Lee ,  Hemanth Jagannathan

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78 ,  H01L21/324 ,  H01L21/225 ,  H01L29/10 ,  H01L27/11

Abstract: A method of reducing the distance between co-linear vertical fin field effect devices is provided. The method includes forming a first vertical fin on a substrate, forming a second vertical fin on the substrate, and depositing a masking block in the gap between the first vertical fin and second vertical fin. The method further includes depositing a spacer layer on the substrate, masking block, first vertical fin, and second vertical fin, depositing a protective liner on the spacer layer, and removing a portion of the protective liner from the spacer layer on the masking block and substrate adjacent to the first vertical fin. The method further includes removing a portion of the spacer layer from a portion the masking block and a portion of the substrate adjacent to the first vertical fin, and growing a first source/drain layer on an exposed portion of the substrate and first vertical fin.

公开(公告)号：US20200279918A1

公开(公告)日：2020-09-03

申请号：US16290611

申请日：2019-03-01

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Dechao Guo ,  Ruqiang Bao ,  Junli Wang ,  Lan Yu ,  Reinaldo Vega ,  Adra Carr

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/02

Abstract: Techniques are provided to fabricate semiconductor devices having a nanosheet field-effect transistor device disposed on a semiconductor substrate. The nanosheet field-effect transistor device includes a nanosheet stack structure including a semiconductor channel layer and a source/drain region in contact with an end portion of the semiconductor channel layer of the nanosheet stack structure. A trench formed in the source/drain region is filled with a metal-based material. The metal-based material filling the trench in the source/drain region mitigates the effect of source/drain material overfill on the contact resistance of the semiconductor device.