公开(公告)号：US20150187737A1

公开(公告)日：2015-07-02

申请号：US14561546

申请日：2014-12-05

Applicant: Industrial Technology Research Institute

Inventor： Yu-Min Lin ,  Chau-Jie Zhan

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  B81B7/00 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/3135 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/37001 ,  Y10T428/24149 ,  H01L2224/81 ,  H01L2924/00

Abstract: A molding package assembly is provided, which includes a substrate and first and second molding packages stacked on the substrate. Each of the first and second molding packages has a semiconductor element, an anti-warping structure disposed around a periphery of the semiconductor element, a molding material encapsulating the semiconductor element and the anti-warping structure, and a protection layer formed on the semiconductor element, the molding material and the anti-warping structure. The anti-warping structure facilitates to prevent warping of the molding package assembly during a molding process.

Abstract translation: 提供了一种成型包装组件，其包括基底和堆叠在基底上的第一和第二模制包装。 第一和第二成型包装件中的每一个具有半导体元件，围绕半导体元件的周围设置的防翘曲结构，封装半导体元件和抗翘曲结构的成型材料以及形成在半导体元件上的保护层 ，成型材料和抗翘曲结构。 防翘曲结构便于在模制过程中防止模制包装组件翘曲。

公开(公告)号：US20240170473A1

公开(公告)日：2024-05-23

申请号：US18347594

申请日：2023-07-06

Applicant: Industrial Technology Research Institute

Inventor： Hao-Che Kao ,  Wen-Hung Liu ,  Yu-Min Lin ,  Ching-Kuan Lee

IPC: H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3121 ,  H01L23/3735 ,  H01L23/49822 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/95 ,  H01L25/0655 ,  H01L21/4853 ,  H01L24/16 ,  H01L24/73 ,  H01L2221/68381 ,  H01L2224/16227 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/33505 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/0665

Abstract: A chip package structure including a heat dissipation base, a first redistribution layer, a second redistribution layer, at least one chip, at least one metal stack, a plurality of conductive structures, and an encapsulant is provided. The second redistribution layer is disposed on the heat dissipation base and thermally coupled to the heat dissipation base. The chip, the metal stack, and the conductive structures are disposed between the second redistribution layer and the first redistribution layer. An active surface of the chip is electrically connected to the first redistribution layer and an inactive surface of the chip is thermally coupled to the second redistribution layer via the metal stack. The first redistribution layer is electrically connected to the second redistribution layer via the conductive structures. The encapsulant is filled between the second redistribution layer and the first redistribution layer. A manufacturing method of a chip package structure is also provided.

公开(公告)号：US11424190B2

公开(公告)日：2022-08-23

申请号：US17005310

申请日：2020-08-27

Applicant: Industrial Technology Research Institute

Inventor： Chao-Jung Chen ,  Yu-Min Lin ,  Sheng-Tsai Wu ,  Shin-Yi Huang ,  Ang-Ying Lin ,  Tzu-Hsuan Ni ,  Yuan-Yin Lo

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065

Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a dielectric body, a plurality of semiconductor bodies separated by the dielectric body, a through via penetrating through the dielectric body, and a wiring structure located in each of the plurality of semiconductor bodies; a plurality of semiconductor chips located side by side on a first surface of the interposer and electrically connected to the wiring structure; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface of the interposer and electrically connected to the plurality of semiconductor chips through the through via.

公开(公告)号：US20210111126A1

公开(公告)日：2021-04-15

申请号：US17065521

申请日：2020-10-08

Applicant: Industrial Technology Research Institute

Inventor： Ang-Ying Lin ,  Yu-Min Lin ,  Shin-Yi Huang ,  Sheng-Tsai Wu ,  Yuan-Yin Lo ,  Tzu-Hsuan Ni ,  Chao-Jung Chen

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00

Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a wiring structure and an interposer via electrically connected to the wiring structure; a plurality of semiconductor chips located on a first surface of the interposer and electrically connected to each other through the interposer; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface, wherein the plurality of semiconductor chips are electrically connected to the redistribution circuit structure through at least the interposer.

公开(公告)号：US20210111125A1

公开(公告)日：2021-04-15

申请号：US17005310

申请日：2020-08-27

Applicant: Industrial Technology Research Institute

Inventor： Chao-Jung Chen ,  Yu-Min Lin ,  Sheng-Tsai Wu ,  Shin-Yi Huang ,  Ang-Ying Lin ,  Tzu-Hsuan Ni ,  Yuan-Yin Lo

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56

Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a dielectric body, a plurality of semiconductor bodies separated by the dielectric body, a through via penetrating through the dielectric body, and a wiring structure located in each of the plurality of semiconductor bodies; a plurality of semiconductor chips located side by side on a first surface of the interposer and electrically connected to the wiring structure; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface of the interposer and electrically connected to the plurality of semiconductor chips through the through via.

公开(公告)号：US10784297B2

公开(公告)日：2020-09-22

申请号：US16194802

申请日：2018-11-19

Applicant: Industrial Technology Research Institute

Inventor： Yu-Min Lin ,  Tao-Chih Chang

IPC: H01L27/146 ,  H01L23/00 ,  H01L23/31

Abstract: A chip scale package structure is provided. The chip scale package structure includes an image sensor chip and a chip. The image sensor chip includes a first redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the first redistribution layer. The chip includes a second redistribution layer including a conductive wire and a conductive pad formed on the conductive wire, wherein the conductive pad is exposed from the surface of the second redistribution layer. The area of the chip is smaller than that of the image sensor chip. The second redistribution layer of the chip bonds to the first redistribution layer of the image sensor chip.

公开(公告)号：US08866309B2

公开(公告)日：2014-10-21

申请号：US13727599

申请日：2012-12-27

Applicant: Industrial Technology Research Institute

Inventor： Jing-Yao Chang ,  Tao-Chih Chang ,  Yu-Wei Huang ,  Yu-Min Lin ,  Shin-Yi Huang

IPC: H01L23/48 ,  H01L29/40

CPC classification number: H01L25/16 ,  H01L23/3121 ,  H01L23/38 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/157 ,  H01L2924/15786 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A first back surface of a first chip faces toward a carrier. A first active surface of the first chip has first pads and a first insulting layer thereon. A second chip is disposed on the first chip and electrically connected to the carrier. A second active surface of the second chip faces toward the first active surface. The second active surface has second pads and a second insulting layer thereon. Bumps connect the first and second pads. First and second daisy chain circuits are respectively disposed on the first and second insulting layers. Hetero thermoelectric device pairs are disposed between the first and second chips and connected in series by the first and second daisy chain circuits, and constitute a circuit with an external device. First and second heat sinks are respectively disposed on a second surface of the carrier and a second back surface of the second chip.

Abstract translation: 第一芯片的第一后表面朝向载体。 第一芯片的第一有源表面具有第一焊盘和其上的第一绝缘层。 第二芯片设置在第一芯片上并电连接到载体。 第二芯片的第二有源表面朝向第一有源表面。 第二活性表面在其上具有第二垫和第二绝缘层。 碰撞连接第一和第二垫。 第一和第二菊花链电路分别设置在第一和第二绝缘层上。 异质热电元件对设置在第一和第二芯片之间并且由第一和第二菊花链电路串联连接，并且构成具有外部装置的电路。 第一和第二散热器分别设置在载体的第二表面和第二芯片的第二后表面上。

公开(公告)号：US20230197680A1

公开(公告)日：2023-06-22

申请号：US17564197

申请日：2021-12-28

Applicant: Industrial Technology Research Institute

Inventor： Po-Kai Chiu ,  Sheng-Tsai Wu ,  Yu-Min Lin ,  Wen-Hung Liu ,  Ang-Ying Lin ,  Chang-Sheng Chen

IPC: H01L25/065 ,  H01L23/367 ,  H01L23/498 ,  H01L23/66 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/367 ,  H01L23/49822 ,  H01L23/66 ,  H01L23/3107 ,  H01L23/49811 ,  H01L24/16 ,  H01L2223/6677 ,  H01L2224/16227

Abstract: An integrated antenna package structure includes a first redistribution structure, a first chip, a heat dissipation structure, a second chip, and an antenna structure. The first chip is located on a first side of the first redistribution structure, and is electrically connected to the first redistribution structure. The heat dissipation structure is thermally connected to the first chip, and the first chip is located between the heat dissipation structure and the first redistribution structure. The second chip is located on a second side of the first redistribution structure opposite to the first side, and is electrically connected to the first redistribution structure. The antenna structure is electrically connected to the first redistribution structure.

公开(公告)号：US20230187409A1

公开(公告)日：2023-06-15

申请号：US18166493

申请日：2023-02-09

Applicant: Industrial Technology Research Institute

Inventor： Yu-Min Lin ,  Ang-Ying Lin ,  Sheng-Tsai Wu ,  Chao-Jung Chen ,  Tzu-Hsuan Ni ,  Shin-Yi Huang ,  Yuan-Yin Lo

IPC: H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56 ,  H01L23/538

CPC classification number: H01L25/0652 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/5383 ,  H01L25/50 ,  H01L2225/06548

Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes a redistribution circuit structure; a first semiconductor chip disposed on the redistribution structure and having a first active surface on which a first conductive post is disposed; a second semiconductor chip disposed above the first semiconductor chip and having a second active surface on which a first conductor is disposed; and a first encapsulant disposed on the redistribution circuit structure and encapsulating at least the first semiconductor chip, wherein the first conductive post and the first conductor are aligned and bonded to each other to electrically connect the first semiconductor chip and the second semiconductor chip.

公开(公告)号：US11646270B2

公开(公告)日：2023-05-09

申请号：US17065521

申请日：2020-10-08

Applicant: Industrial Technology Research Institute

Inventor： Ang-Ying Lin ,  Yu-Min Lin ,  Shin-Yi Huang ,  Sheng-Tsai Wu ,  Yuan-Yin Lo ,  Tzu-Hsuan Ni ,  Chao-Jung Chen

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5386 ,  H01L21/481 ,  H01L21/486 ,  H01L21/4857 ,  H01L23/5383 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/24 ,  H01L24/73 ,  H01L23/3185 ,  H01L2224/1357 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/16225 ,  H01L2224/16505 ,  H01L2224/1703 ,  H01L2224/2402 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/73204 ,  H01L2224/73209

Abstract: A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a wiring structure and an interposer via electrically connected to the wiring structure; a plurality of semiconductor chips located on a first surface of the interposer and electrically connected to each other through the interposer; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface, wherein the plurality of semiconductor chips are electrically connected to the redistribution circuit structure through at least the interposer.