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公开(公告)号：US20190155370A1
公开(公告)日：2019-05-23
申请号：US16252816
申请日：2019-01-21
Applicant: Intel Corporation
Inventor： Sundar Ramani , Arvind Raman , Arvind Mandhani , Ashish V. Choubal , Kalyan Muthukumar , Ajaya V. Durg , Samudyatha Chakki
IPC: G06F1/3287 , G06F1/3296 , G06F1/3203 , G06F12/0804 , G06F12/084 , G06F12/128 , G06F12/0831 , G06F12/0808 , G06F1/324 , G06F1/3234 , G06F12/0815
Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.
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公开(公告)号：US20170177046A1
公开(公告)日：2017-06-22
申请号：US14970747
申请日：2015-12-16
Applicant: Intel Corporation
Inventor： Vivek Garg , Alexander Gendler , Arvind Raman , Ashish V. Choubal , Krishnakanth V. Sistla , Dean Mulla , Eric J. Dehaemer , Rahul Agrawal , Guy G. Sotomayor
IPC: G06F1/26
CPC classification number: G06F1/26 , G06F1/3243 , Y02D10/152
Abstract: In one embodiment, a processor includes cores to execute instructions. At least some of the cores include a telemetry data control logic to send a first telemetry data packet to a power controller according to a stagger schedule to prevent data collisions, and a global alignment counter to count a stagger alignment period. Other embodiments are described and claimed.
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公开(公告)号：US09665153B2
公开(公告)日：2017-05-30
申请号：US14221696
申请日：2014-03-21
Applicant: Intel Corporation
Inventor： Sundar Ramani , Arvind Raman , Arvind Mandhani , Ashish V. Choubal , Kalyan Muthukumar , Ajaya V. Durg , Samudyatha Chakki
IPC: G06F1/32 , G06F12/0815 , G06F12/0804 , G06F12/084 , G06F12/0811
CPC classification number: G06F1/3287 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3275 , G06F1/3296 , G06F12/0804 , G06F12/0808 , G06F12/0811 , G06F12/0815 , G06F12/0831 , G06F12/084 , G06F12/128 , G06F2212/1028 , G06F2212/314 , G06F2212/621 , G06F2212/69 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D10/152 , Y02D10/172 , Y02D50/20
Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.
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14.发明授权公开(公告)号：US12086653B2
公开(公告)日：2024-09-10
申请号：US17134065
申请日：2020-12-24
Applicant: Intel Corporation
Inventor： Vedvyas Shanbhogue , Jeff A. Huxel , Jeffrey G. Wiedemeier , James D. Allen , Arvind Raman , Krishnakumar Ganapathy
CPC classification number: G06F9/52 , G06F9/30101 , G06F9/3885 , G06F11/0724 , G06F11/0751 , G06F11/0772 , G06F11/1629 , G06F11/1683 , G06F9/45558
Abstract: A processor is described. The processor includes model specific register space that is visible to software above a BIOS level. The model specific register space is to specify a granularity of a processing entity of a lock-step group. The processor also includes logic circuitry to support dynamic entry/exit of the lock-step group's processing entities to/from lock-step mode including: i) termination of lock-step execution by the processing entities before the program code to be executed in lock-step is fully executed; and, ii) as part of the exit from the lock-step mode, restoration of a state of a shadow processing entity of the processing entities as the state existed before the shadow processing entity entered the lock-step mode and began lock-step execution of the program code.
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公开(公告)号：US12007826B2
公开(公告)日：2024-06-11
申请号：US17128076
申请日：2020-12-19
Applicant: Intel Corporation
Inventor： Charles Augustine , Pascal Meinerzhagen , Suyoung Bang , Abdullah Afzal , Karthik Subramanian , Muhammad Khellah , Arvind Raman
IPC: G06F1/32 , G06F1/08 , G06F1/10 , G06F1/12 , G06F1/324 , G06F1/3296 , H03K19/0175
CPC classification number: G06F1/324 , G06F1/08 , G06F1/12 , G06F1/3296 , H03K19/017509
Abstract: Described is a controller that provides in-situ state retention using a closed loop global retention clamp. The controller addresses di/dt and reliability constraints using an adaptive scheme where steps with smaller current are quickly changed whereas steps with larger current are changed slowly. The loop controller of a voltage regulator is modified for controlling not only retention Vmin during a low power state (e.g., C1LP), but also to control fast wake up the low power state (e.g., from C1LP and from C6).
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Patent Agency Ranking
公开(公告)号：US11320888B2
公开(公告)日：2022-05-03
申请号：US16124071
申请日：2018-09-06
Applicant: Intel Corporation
Inventor： Charles Augustine , Muhammad Khellah , Arvind Raman , Ashish Choubal , Karthik Subramanian , Abdullah Afzal , Feroze Merchant
IPC: G06F1/00 , G06F1/3234 , H02M3/157 , G06F1/324 , H02M1/00
Abstract: An apparatus is provided which comprises: a plurality of devices coupled to an input power supply rail and an output power supply rail; a first circuitry coupled to the plurality of devices, wherein the first circuitry is to turn on or off one or more devices of the plurality according to a control; and a second circuitry coupled to the first circuitry, wherein the second circuitry comprises an all-digital proportional-derivative mechanism to generate the control according to a digital representation of voltage on the output power supply rail.
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公开(公告)号：US10963038B2
公开(公告)日：2021-03-30
申请号：US16252816
申请日：2019-01-21
Applicant: Intel Corporation
Inventor： Sundar Ramani , Arvind Raman , Arvind Mandhani , Ashish V. Choubal , Kalyan Muthukumar , Ajaya V. Durg , Samudyatha Chakki
IPC: G06F1/32 , G06F1/3287 , G06F1/3203 , G06F1/3296 , G06F12/0815 , G06F12/0804 , G06F12/084 , G06F1/324 , G06F1/3234 , G06F12/0808 , G06F12/0831 , G06F12/128 , G06F12/0811 , G06F12/12
Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.
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公开(公告)号：US20200081512A1
公开(公告)日：2020-03-12
申请号：US16124071
申请日：2018-09-06
Applicant: Intel Corporation
Inventor： Charles Augustine , Muhammad Khellah , Arvind Raman , Ashish Choubal , Karthik Subramanian , Abdullah Afzal , Feroze Merchant
Abstract: An apparatus is provided which comprises: a plurality of devices coupled to an input power supply rail and an output power supply rail; a first circuitry coupled to the plurality of devices, wherein the first circuitry is to turn on or off one or more devices of the plurality according to a control; and a second circuitry coupled to the first circuitry, wherein the second circuitry comprises an all-digital proportional-derivative mechanism to generate the control according to a digital representation of voltage on the output power supply rail.
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公开(公告)号：US09910470B2
公开(公告)日：2018-03-06
申请号：US14970747
申请日：2015-12-16
Applicant: Intel Corporation
Inventor： Vivek Garg , Alexander Gendler , Arvind Raman , Ashish V. Choubal , Krishnakanth V. Sistla , Dean Mulla , Eric J. Dehaemer , Rahul Agrawal , Guy G. Sotomayor
CPC classification number: G06F1/26 , G06F1/3243 , Y02D10/152
Abstract: In one embodiment, a processor includes cores to execute instructions. At least some of the cores include a telemetry data control logic to send a first telemetry data packet to a power controller according to a stagger schedule to prevent data collisions, and a global alignment counter to count a stagger alignment period. Other embodiments are described and claimed.
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公开(公告)号：US09625984B2
公开(公告)日：2017-04-18
申请号：US14671750
申请日：2015-03-27
Applicant: Intel Corporation
Inventor： Aswin Ramachandran , Arvind Raman
CPC classification number: G06F1/3287 , G06F1/3203 , G06F1/3228 , G06F1/324 , G06F1/3296 , G06F9/4418 , G06F11/0724 , Y02D10/126 , Y02D10/171 , Y02D10/172
Abstract: Technologies of managing power during an activation cycle of a processor core or other compute domain include determining new operation limits for active processor cores or other compute domains during an activation cycle of a hibernating processor core or other hibernating compute domain to reduce the likelihood of a power surge during the activation of the hibernating processor core or other compute domain. The active processor cores or other compute domain are monitored until their operating points are at or below the new operating limits. Thereafter, the hibernating processor core or other hibernating compute domain is activated.
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