公开(公告)号：US11315843B2

公开(公告)日：2022-04-26

申请号：US16472837

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Yi Elyn Xu ,  Bilal Khalaf ,  Dennis Sean Carr

IPC: H01L23/48 ,  H01L23/13 ,  H01L21/48 ,  H01L23/498 ,  H01L25/16

Abstract: Various embodiments disclosed relate to a substrate for a semiconductor device. The substrate includes a first major surface and a second major surface opposite the first major surface. The substrate further includes a cavity defined by a portion of the first major surface. The cavity includes a bottom dielectric surface and a plurality of sidewalls extending from the bottom surface to the first major surface. A first portion of a first sidewall includes a conductive material.

公开(公告)号：US11145632B2

公开(公告)日：2021-10-12

申请号：US16636616

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Juan E. Dominguez ,  Hyoung Il Kim ,  Bilal Khalaf ,  John Gary Meyers

IPC: H01L25/10 ,  H01L23/31 ,  H01L25/065

Abstract: A high density die package configuration is shown for use on system boards. In one example, an apparatus includes a system board, a first package mounted to the system board, a second package mounted to the system board, and an interface package mounted between the first and the second package and coupled directly to the first package and to the second package through the respective first and second packages.

公开(公告)号：US10090261B2

公开(公告)日：2018-10-02

申请号：US15471942

申请日：2017-03-28

Applicant: INTEL CORPORATION

Inventor： Florence R. Pon ,  Bilal Khalaf ,  Saeed S. Shojaie

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/544 ,  H01L21/78 ,  H01L23/31

Abstract: A microelectronic package may be fabricated with debug access ports formed either at a side or at a bottom of the microelectronic package. In one embodiment, the debug access ports may be formed within an encapsulation material proximate the microelectronic package side. In another embodiment, the debug access ports may be formed in a microelectronic interposer of the microelectronic package proximate the microelectronic package side. In a further embodiment, the debug access ports may be formed at the microelectronic package bottom and may include a solder contact.

公开(公告)号：US11710674B2

公开(公告)日：2023-07-25

申请号：US17707094

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Yi Elyn Xu ,  Bilal Khalaf ,  Dennis Sean Carr

IPC: H01L23/48 ,  H01L23/13 ,  H01L21/48 ,  H01L23/498 ,  H01L25/16

CPC classification number: H01L23/13 ,  H01L21/4846 ,  H01L23/49838 ,  H01L25/16

Abstract: Various embodiments disclosed relate to a substrate for a semiconductor device. The substrate includes a first major surface and a second major surface opposite the first major surface. The substrate further includes a cavity defined by a portion of the first major surface. The cavity includes a bottom dielectric surface and a plurality of sidewalls extending from the bottom surface to the first major surface. A first portion of a first sidewall includes a conductive material.

公开(公告)号：US11700696B2

公开(公告)日：2023-07-11

申请号：US17338450

申请日：2021-06-03

Applicant: Intel Corporation

Inventor： Florence R. Neumann ,  Bilal Khalaf ,  Saeed S. Shojaie

IPC: H05K1/18 ,  H05K3/28 ,  G01R31/28

CPC classification number: H05K3/284 ,  G01R31/2818 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Embodiments are generally directed to a buried electrical debug access port. An embodiment of an apparatus includes a substrate or printed circuit board; one or more electronic components coupled with the substrate or printed circuit board; one or more electrical access ports coupled with the substrate or printed circuit board, each electrical access port including electrically conductive material; and an encapsulant material, the encapsulant material encapsulating the one or more access ports, wherein the one or more access ports are electrically connected to one or more circuits of the apparatus to provide debugging access to the apparatus.

公开(公告)号：US11329027B2

公开(公告)日：2022-05-10

申请号：US16087543

申请日：2016-04-26

Applicant: Intel Corporation

Inventor： Bilal Khalaf

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A microelectronic package may be fabricated having a microelectronic die stack attached to a microelectronic substrate and at least one microelectronic device, which is separate from the microelectronic die stack, attached to the microelectronic substrate within the footprint of one of the microelectronic dice within the microelectronic die stack. In one embodiment, the microelectronic die stack may have a plurality of stacked microelectronic dice, wherein one microelectronic die of the plurality of microelectronic dice has a footprint greater than the other microelectronic die of the plurality of microelectronic dice, and wherein the at least one microelectronic device is attached to the one microelectronic die of the plurality of microelectronic dice having the greater footprint.

公开(公告)号：US20210074668A1

公开(公告)日：2021-03-11

申请号：US16306879

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Bilal Khalaf ,  Mao Guo

IPC: H01L23/00 ,  H01L25/065

Abstract: Electronic device package technology is disclosed. In one example, an electronic device includes a substrate having a bond finger, a die coupled to the substrate and having a bond pad, a first bond wire coupled between the bond pad and the bond finger, and a second bond wire coupled between the bond pad and the bond finger. The first bond wire is reverse bonded between a pad solder ball on the bond pad and a finger solder ball on the bond finger. The second bond wire is forward bonded between a supplemental pad solder ball on the pad solder and the bond finger adjacent the finger solder ball. Associated systems and methods are also disclosed.

公开(公告)号：US09972610B2

公开(公告)日：2018-05-15

申请号：US14809132

申请日：2015-07-24

Applicant: Intel Corporation

Inventor： Bilal Khalaf

IPC: G11C7/00 ,  H01L25/18 ,  H01L25/00 ,  G06F3/06

CPC classification number: H01L25/18 ,  G06F3/0604 ,  G06F3/0629 ,  G06F3/0673 ,  H01L23/538 ,  H01L25/50 ,  H01L2224/16225

Abstract: Techniques and mechanisms for a SIP to control access to a non-volatile memory of another packaged device. In an embodiment, the SIP includes interface a processor, a local memory and a memory controller that provides the processor with access to the local memory. The SIP further includes interface hardware to couple the SIP to the packaged device, wherein the processor of the SIP accesses a non-volatile memory of the packaged device via the memory controller of the SIP. In another embodiment, the interface hardware of the SIP includes a first plurality of contacts to couple to the packaged device, as well as a second plurality of contacts. An interface standard describe an arrangement of interface contacts, wherein, of a first arrangement of the first contacts and the second arrangement of the second contacts, only the second arrangement conforms to the described arrangement of interface contacts.

公开(公告)号：US09646952B2

公开(公告)日：2017-05-09

申请号：US14857317

申请日：2015-09-17

Applicant: INTEL CORPORATION

Inventor： Florence R. Pon ,  Bilal Khalaf ,  Saeed S. Shojaie

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/573 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/544 ,  H01L25/0652 ,  H01L2223/54453 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A microelectronic package may be fabricated with debug access ports formed either at a side or at a bottom of the microelectronic package. In one embodiment, the debug access ports may be formed within an encapsulation material proximate the microelectronic package side. In another embodiment, the debug access ports may be formed in a microelectronic interposer of the microelectronic package proximate the microelectronic package side. In a further embodiment, the debug access ports may be formed at the microelectronic package bottom and may include a solder contact.

公开(公告)号：US11811182B2

公开(公告)日：2023-11-07

申请号：US16157184

申请日：2018-10-11

Applicant: Intel Corporation

Inventor： Tyler Leuten ,  Mohammed Rahman ,  Bilal Khalaf

IPC: H01R4/58 ,  H01L23/498 ,  H05K1/18 ,  H01R4/04 ,  H01R4/48 ,  H05K3/32 ,  H01R43/027

CPC classification number: H01R4/58 ,  H01L23/49816 ,  H01L23/49866 ,  H01R4/04 ,  H01R4/48 ,  H05K1/181 ,  H05K3/321 ,  H05K3/325 ,  H01R43/027 ,  H05K2201/10393 ,  H05K2201/10598 ,  H05K2201/10734 ,  H05K2201/10909

Abstract: Embodiments disclosed herein include electronics packages and methods of forming such packages. In an embodiment, the electronics package comprises a first substrate and a plurality of first conductive pads on the first substrate. In an embodiment, the electronics package further comprises a second substrate and a plurality of second conductive pads on the second substrate. In an embodiment, the electronics package further comprises a plurality of interconnects between the first and second substrate. In an embodiment, each interconnect electrically couples one of the first conductive pads to one of the second conductive pads. In an embodiment, the interconnects comprise strands of conductive material that are woven on themselves to form a mesh-like structure.