公开(公告)号：US20170194469A1

公开(公告)日：2017-07-06

申请号：US15466715

申请日：2017-03-22

Applicant: Intel Corporation

Inventor： GILBERT DEWEY ,  MARKO RADOSAVLJEVIC ,  RAVI PILLARISETTY ,  MATTHEW V. METZ

IPC: H01L29/775 ,  H01L29/15 ,  H01L29/205 ,  H01L29/786 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/155 ,  H01L29/205 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66469 ,  H01L29/78681 ,  H01L29/78696

Abstract: Semiconductor devices having group III-V material active regions and graded gate dielectrics and methods of fabricating such devices are described. In an example, a semiconductor device includes a group III-V material channel region disposed above a substrate. A gate stack is disposed on the group III-V material channel region. The gate stack includes a graded high-k gate dielectric layer disposed directly between the III-V material channel region and a gate electrode. The graded high-k gate dielectric layer has a lower dielectric constant proximate the III-V material channel region and has a higher dielectric constant proximate the gate electrode. Source/drain regions are disposed on either side of the gate stack.

公开(公告)号：US20150076571A1

公开(公告)日：2015-03-19

申请号：US14552959

申请日：2014-11-25

Applicant: Intel Corporation

Inventor： NILOY MUKHERJEE ,  GILBERT DEWEY ,  MATTHEW V. METZ ,  JACK T. KAVALIEROS ,  ROBERT S. CHAU

IPC: H01L29/51 ,  H01L29/78

CPC classification number: H01L29/517 ,  H01L21/285 ,  H01L21/28512 ,  H01L21/76831 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/0895 ,  H01L29/41791 ,  H01L29/452 ,  H01L29/456 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A contact to a source or drain region. The contact has a conductive material, but that conductive material is separated from the source or drain region by an insulator.

Abstract translation: 与源极或漏极区的接触。 接触件具有导电材料，但是导电材料通过绝缘体与源极或漏极区域分离。

公开(公告)号：US20180337235A1

公开(公告)日：2018-11-22

申请号：US15776996

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： WILLY RACHMADY ,  MATTHEW V. METZ ,  GILBERT DEWEY ,  CHANDRA S. MOHAPATRA ,  NADIA M. RAHHAL-ORABI ,  Jack T. KAVALIEROS ,  ANAND S. MURTHY ,  TAHIR GHANI

IPC: H01L29/10 ,  H01L29/205 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/205 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: Embodiments of the present disclosure describe a semiconductor multi-gate transistor having a semi-conductor fin extending from a substrate and including a sub-fin region and an active region. The subfin region may include a dielectric material region under the gate to provide improved isolation. The dielectric material region may be formed during a replacement gate process by replacing a portion of a sub-fin region under the gate with the dielectric material region, followed by fabrication of a replacement gate structure. The sub-fin region may be comprised of group III-V semiconductor materials in various combinations and concentrations. The active region may be comprised of a different group III-V semiconductor material. The dielectric material region may be comprised of amorphous silicon. Other embodiments may be described and/or claimed.

公开(公告)号：US20180323310A1

公开(公告)日：2018-11-08

申请号：US15529432

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： HAROLD W. KENNEL ,  MATTHEW V. METZ ,  WILLY RACHMADY ,  GILBERT DEWEY ,  CHANDRA S. MOHAPATRA ,  ANAND S. MURTHY ,  JACK T. KAVALIEROS ,  TAHIR GHANI

IPC: H01L29/786 ,  H01L29/10 ,  H01L29/78 ,  H01L29/778 ,  H01L27/06

CPC classification number: H01L29/78681 ,  H01L27/0605 ,  H01L29/1054 ,  H01L29/7783 ,  H01L29/78 ,  H01L29/785

Abstract: Semiconductor devices including a subfin including a first III-V semiconductor alloy and a channel including a second III-V semiconductor alloy are described. In some embodiments the semiconductor devices include a substrate including a trench defined by at least two trench sidewalls, wherein the first III-V semiconductor alloy is deposited on the substrate within the trench and the second III-V semiconductor alloy is epitaxially grown on the first III-V semiconductor alloy. In some embodiments, a conduction band offset between the first III-V semiconductor alloy and the second III-V semiconductor alloy is greater than or equal to about 0.3 electron volts. Methods of making such semiconductor devices and computing devices including such semiconductor devices are also described.

公开(公告)号：US20170358645A1

公开(公告)日：2017-12-14

申请号：US15525269

申请日：2014-12-26

Applicant: INTEL CORPORATION

Inventor： GILBERT DEWEY ,  MATTHEW V. METZ ,  JACK T. KAVALIEROS ,  WILLY RACHMADY ,  TAHIR GHANI ,  ANAND S. MURTHY ,  CHANDRA S. MOHAPATRA ,  SANAZ K. GARDNER ,  MARKO RADOSAVLJEVIC ,  GLENN A. GLASS

IPC: H01L29/06 ,  H01L29/12 ,  H01L29/66 ,  H01L21/762 ,  H01L21/311 ,  H01L29/78 ,  H01L29/775 ,  H01L21/306 ,  H01L21/02 ,  H01L29/20 ,  H01L29/161 ,  H01L29/04

CPC classification number: H01L29/0673 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02461 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/7605 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/122 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66469 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: An integrated circuit die includes a quad-gate device nanowire of channel material for a transistor (e.g., single material or stack to be a channel of a MOS device) formed by removing a portion of a sub-fin material from below the channel material, where the sub-fin material was grown in an aspect ration trapping (ART) trench. In some cases, in the formation of such nanowires, it is possible to remove the defective fin material or area under the channel. Such removal isolates the fin channel, removes the fin defects and leakage paths, and forms the nanowire of channel material having four exposed surfaces upon which gate material may be formed.

公开(公告)号：US20170345900A1

公开(公告)日：2017-11-30

申请号：US15527221

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： HAROLD W. KENNEL ,  MATTHEW V. METZ ,  WILLY RACHMADY ,  GILBERT DEWEY ,  CHANDRA S. MOHAPATRA ,  ANAND S. MURTHY ,  JACK T. KAVALIEROS ,  TAHIR GHANI

IPC: H01L29/205 ,  H01L21/02 ,  H01L21/18

CPC classification number: H01L29/205 ,  H01L21/02455 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/182 ,  H01L21/185

Abstract: Semiconductor devices including a subfin including a first III-V compound semiconductor and a channel including a second III-V compound semiconductor are described. In some embodiments the semiconductor devices include a substrate including a trench defined by at least two trench sidewalls, wherein the first III-V compound semiconductor is deposited on the substrate within the trench and the second III-V compound semiconductor is epitaxially grown on the first III-V compound semiconductor. In some embodiments, a conduction band offset between the first III-V compound semiconductor and the second III-V compound semiconductor is greater than or equal to about 0.3 electron volts. Methods of making such semiconductor devices and computing devices including such semiconductor devices are also described.

公开(公告)号：US20170323962A1

公开(公告)日：2017-11-09

申请号：US15525164

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： GILBERT DEWEY ,  MATTHEW V. METZ ,  JACK T. KAVALIEROS ,  WILLY RACHMADY ,  TAHIR GHANI ,  ANAND S. MURTHY ,  CHANDRA S. MOHAPATRA ,  HAROLD W. KENNEL ,  GLENN A. GLASS

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/267

CPC classification number: H01L29/785 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/7781

Abstract: An embodiment includes a device comprising: a trench that includes a doped trench material having: (a)(i) a first bulk lattice constant and (a)(ii) at least one of a group III-V material and a group IV material; a fin structure, directly over the trench, including fin material having: (b) (ii) a second bulk lattice constant and (b)(ii) at least one of a group III-V material and a group IV material; a barrier layer, within the trench and directly contacting a bottom surface of the fin, including a barrier layer material having a third bulk lattice constant; wherein (a) the trench has an aspect ratio (depth to width) of at least 1.5:1, and (b) the barrier layer has a height not greater than a critical thickness for the barrier layer material. Other embodiments are described herein.

公开(公告)号：US20170125524A1

公开(公告)日：2017-05-04

申请号：US15405182

申请日：2017-01-12

Applicant: Intel Corporation

Inventor： RAVI PILLARISETTY ,  SANSAPTAK DASGUPTA ,  NITI GOEL ,  VAN H. LE ,  MARKO RADOSAVLJEVIC ,  GILBERT DEWEY ,  NILOY MUKHERJEE ,  MATTHEW V. METZ ,  WILLY RACHMADY ,  JACK T. KAVALIEROS ,  BENJAMIN CHU-KUNG ,  HAROLD W. KENNEL ,  STEPHEN M. CEA ,  ROBERT S. CHAU

IPC: H01L29/10 ,  H01L29/165 ,  H01L29/20 ,  H01L21/762 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/16 ,  H01L29/267

CPC classification number: H01L29/785 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7851

Abstract: Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin.

公开(公告)号：US20160197173A1

公开(公告)日：2016-07-07

申请号：US14912887

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： GILBERT DEWEY ,  MARKO RADOSAVLJEVIC ,  RAVI PILLARISETTY ,  MATTHEW V. METZ

IPC: H01L29/775 ,  H01L29/15 ,  H01L29/49 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/205

CPC classification number: H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/155 ,  H01L29/205 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66469 ,  H01L29/78681 ,  H01L29/78696

Abstract: Semiconductor devices having group III-V material active regions and graded gate dielectrics and methods of fabricating such devices are described. In an example, a semiconductor device includes a group III-V material channel region disposed above a substrate. A gate stack is disposed on the group III-V material channel region. The gate stack includes a graded high-k gate dielectric layer disposed directly between the III-V material channel region and a gate electrode. The graded high-k gate dielectric layer has a lower dielectric constant proximate the III-V material channel region and has a higher dielectric constant proximate the gate electrode. Source/drain regions are disposed on either side of the gate stack.

Abstract translation: 描述具有III-V族材料活性区域和渐变栅极电介质的半导体器件及其制造方法。 在一个示例中，半导体器件包括设置在衬底上方的III-V族材料沟道区。 栅极叠层设置在III-V族材料沟道区上。 栅堆叠包括直接设置在III-V材料沟道区和栅电极之间的渐变高k栅介质层。 渐变的高k栅极电介质层在III-V材料沟道区附近具有较低的介电常数，并且在栅电极附近具有更高的介电常数。 源极/漏极区域设置在栅极堆叠的两侧。

公开(公告)号：US20200294998A1

公开(公告)日：2020-09-17

申请号：US16355195

申请日：2019-03-15

Applicant: INTEL CORPORATION

Inventor： AARON D. LILAK ,  EHREN MANNEBACH ,  ANH PHAN ,  RICHARD E. SCHENKER ,  STEPHANIE A. BOJARSKI ,  WILLY RACHMADY ,  PATRICK R. MORROW ,  JEFFERY D. BIELEFELD ,  GILBERT DEWEY ,  HUI JAE YOO

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/532

Abstract: Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.