公开(公告)号：US20220006459A1

公开(公告)日：2022-01-06

申请号：US17479963

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Miguel Bautista Gabriel ,  Sriram Vangal ,  Patrick Koeberl ,  Pratik Patel ,  Muhammad Khellah ,  James Tschanz ,  Carlos Tokunaga ,  Suyoung Bang

IPC: H03K19/17768 ,  H03K19/17784 ,  H03K19/0185 ,  H03K19/0175 ,  G01R31/28

Abstract: A detection circuit includes a tunable delay circuit that generates a delayed signal and that receives a supply voltage. The detection circuit includes a control circuit that adjusts a delay provided by the tunable delay circuit to the delayed signal. The detection circuit includes a time-to-digital converter circuit that converts the delay provided by the tunable delay circuit to the delayed signal to a digital code and adjusts the digital code based on changes in the supply voltage. The control circuit causes the tunable delay circuit to maintain the delay provided to the delayed signal constant in response to the digital code reaching an alignment value. The detection circuit may continuously monitor timing margin of a data signal relative to a clock signal and update the digital code in every clock cycle. The detection circuit may be a security sensor that detects changes in the supply voltage.

公开(公告)号：US10217509B2

公开(公告)日：2019-02-26

申请号：US15495954

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Jaydeep P. Kulkarni ,  Bibiche M. Geuskens ,  James Tschanz ,  Vivek K. De ,  Muhammad M. Khellah

IPC: G11C11/419 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/412 ,  G11C11/417 ,  G11C5/14

Abstract: Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.

公开(公告)号：US10122347B2

公开(公告)日：2018-11-06

申请号：US15477913

申请日：2017-04-03

Applicant: Intel Corporation

Inventor： Minki Cho ,  Jaydeep Kulkarni ,  Carlos Tokunaga ,  Muhammad Khellah ,  James Tschanz

IPC: G11C7/00 ,  G11C7/12 ,  H03K3/011 ,  H03K3/012 ,  G11C11/419 ,  G06F1/32

Abstract: An apparatus is provided which includes: a first power supply node; a second power supply node; a memory bit-cell coupled to the second power supply node; a circuitry coupled to the first and second power supply nodes, the circuitry to operate in a diode-connected mode; and a transistor coupled in parallel to the circuitry, wherein the transistor is controllable by a digital signal such that when the transistor is to turn on, it is to apply voltage and/or current stress to the memory bit-cell.

公开(公告)号：US09720484B2

公开(公告)日：2017-08-01

申请号：US14666165

申请日：2015-03-23

Applicant: Intel Corporation

Inventor： Ming Zhang ,  Chris Wilkerson ,  Greg Taylor ,  Randy J. Aksamit ,  James Tschanz

IPC: G06F1/26 ,  G06F1/32 ,  G06F12/0802

CPC classification number: G06F1/324 ,  G06F1/26 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3225 ,  G06F1/3275 ,  G06F1/3293 ,  G06F12/0802 ,  G06F2212/1028 ,  Y02D10/13

Abstract: Disclosed herein are approaches to reducing a guardband (margin) used for minimum voltage supply (Vcc) requirements for memory such as cache.

公开(公告)号：US09633716B2

公开(公告)日：2017-04-25

申请号：US14989762

申请日：2016-01-06

Applicant: Intel Corporation

Inventor： Jaydeep P. Kulkarni ,  Bibiche M. Geuskens ,  James Tschanz ,  Vivek K. De ,  Muhammed M. Khellah

IPC: G11C11/419 ,  G11C8/08 ,  G11C11/417 ,  G11C7/12 ,  G11C8/10 ,  G11C11/418 ,  G11C13/00 ,  G11C5/14 ,  G11C29/02 ,  G11C11/412 ,  G11C11/4074

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C5/148 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4074 ,  G11C11/412 ,  G11C11/417 ,  G11C11/418 ,  G11C13/0038 ,  G11C29/021 ,  G11C29/028 ,  G11C2207/2227

Abstract: Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.

公开(公告)号：US09015507B2

公开(公告)日：2015-04-21

申请号：US14038639

申请日：2013-09-26

Applicant: Intel Corporation

Inventor： Ming Zhang ,  Chris Wilkerson ,  Greg Taylor ,  Randy J. Aksamit ,  James Tschanz

IPC: G06F1/32 ,  G06F1/26 ,  G06F12/08

CPC classification number: G06F1/324 ,  G06F1/26 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3225 ,  G06F1/3275 ,  G06F1/3293 ,  G06F12/0802 ,  G06F2212/1028 ,  Y02D10/13

Abstract: Disclosed herein are approaches to reducing a guardband (margin) used for minimum voltage supply (Vcc) requirements for memory such as cache.

Abstract translation: 这里公开了减少用于诸如高速缓存的存储器的最小电压供应（Vcc）要求的保护带（余量）的方法。