公开(公告)号：US20200185226A1

公开(公告)日：2020-06-11

申请号：US16334324

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Kevin LIN ,  Rahim KASIM ,  Manish CHANDHOK ,  Florian Gstrein

IPC: H01L21/302 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

Abstract: Techniques for selectively removing a metal or conductive material during processing of a semiconductor die for high-voltage applications are provided. In some embodiments, the techniques treat a metallized semiconductor die to transfer a feature from a patterned photoresist layer deposited on the metallized semiconductor die. In addition, the patterned metallized semiconductor die can be subjected to an etch process to remove an amount of metal according to the feature in the pattern, resulting in a treated metallized semiconductor die that defines an opening adjacent to at least a pair of neighboring metal interconnects in the die. The treated metallized semiconductor die can be further treated to backfill the opening with a dielectric material, resulting in a metallized semiconductor die having a backfilled dielectric member. Such a metallized semiconductor die can be further processed according to a process of record until metallization, after which additional selective removal of another amount of metal can be implemented. Semiconductor dies having neighboring metal interconnects separated by backfilled dielectric regions also are provided.

公开(公告)号：US20190019748A1

公开(公告)日：2019-01-17

申请号：US16069154

申请日：2016-03-28

Applicant: Intel Corporation

Inventor： Charles H. WALLACE ,  Leonard P. GULER ,  Manish CHANDHOK ,  Paul A. NYHUS

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/5329

Abstract: Pitch division patterning approaches with increased overlay margin for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, a method includes forming a first plurality of conductive lines in a first sacrificial material formed above a substrate. The first plurality of conductive lines is formed along a direction of a BEOL metallization layer and is spaced apart by a pitch. The method also includes removing the first sacrificial material, forming a second sacrificial material adjacent to sidewalls of the first plurality of conductive lines, and then forming a second plurality of conductive lines adjacent the second sacrificial material. The second plurality of conductive lines is formed along the direction of the BEOL metallization layer, is spaced apart by the pitch, and is alternating with the first plurality of conductive lines. The method also includes removing the second sacrificial layer.

公开(公告)号：US20180323078A1

公开(公告)日：2018-11-08

申请号：US15774255

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Stephanie A. BOJARSKI ,  Manish CHANDHOK ,  Todd R. YOUNKIN ,  Eungnak HAN ,  Kranthi Kumar ELINENI ,  Ashish N. GAIKWAD ,  Paul A. NYHUS ,  Charles H. WALLACE ,  Hui Jae YOO

IPC: H01L21/311 ,  H01L21/033

CPC classification number: H01L21/31144 ,  G03F7/0002 ,  H01L21/0337 ,  H01L21/0338

Abstract: A method including forming a target pattern of a target material on a surface of a substrate; depositing a block copolymer on the surface of the substrate, wherein one of two blocks of the block copolymer preferentially aligns to the target material and the two blocks self assemble after deposition into repeating lamellar bodies on the surface of the substrate; selectively retaining one of the two blocks of the block copolymer over the other as a polymer pattern; and patterning the substrate with the polymer pattern. An apparatus including an integrated circuit substrate including a plurality of contact points and a dielectric layer on the contact points; a target pattern formed in a surface of the dielectric layer; and a self-assembled layer of repeating alternating bodies of a block copolymer, wherein one of two blocks of the block copolymer is preferentially aligned to the target pattern.

公开(公告)号：US20240071917A1

公开(公告)日：2024-02-29

申请号：US18384582

申请日：2023-10-27

Applicant: Intel Corporation

Inventor： Richard E. SCHENKER ,  Robert L. BRISTOL ,  Kevin L. LIN ,  Florian GSTREIN ,  James M. BLACKWELL ,  Marie KRYSAK ,  Manish CHANDHOK ,  Paul A. NYHUS ,  Charles H. WALLACE ,  Curtis W. WARD ,  Swaminathan SIVAKUMAR ,  Elliot N. TAN

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L27/0886 ,  H01L29/7848

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

公开(公告)号：US20240047543A1

公开(公告)日：2024-02-08

申请号：US18382339

申请日：2023-10-20

Applicant: Intel Corporation

Inventor： Rami HOURANI ,  Richard VREELAND ,  Giselle ELBAZ ,  Manish CHANDHOK ,  Richard E. SCHENKER ,  Gurpreet SINGH ,  Florian GSTREIN ,  Nafees KABIR ,  Tristan A. TRONIC ,  Eungnak HAN

IPC: H01L29/423 ,  H01L29/78 ,  H01L23/522 ,  H01L29/417 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/4238 ,  H01L29/7851 ,  H01L23/5226 ,  H01L29/41775 ,  H01L27/0886 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823468 ,  H01L21/823431

Abstract: Contact over active gate structures with metal oxide cap structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a metal oxide cap structure thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on a portion of one or more of the metal oxide cap structures.

公开(公告)号：US20230095402A1

公开(公告)日：2023-03-30

申请号：US17485190

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Manish CHANDHOK ,  Elijah V. KARPOV ,  Mohit K. HARAN ,  Reken PATEL ,  Charles H. WALLACE ,  Gurpreet SINGH ,  Florian GSTREIN ,  Eungnak HAN ,  Urusa ALAAN ,  Leonard P. GULER ,  Paul A. NYHUS

IPC: H01L21/768 ,  H01L29/78 ,  H01L23/535 ,  H01L29/66

Abstract: Contact over active gate (COAG) structures with conductive trench contact taps are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. One of the plurality of conductive trench contact structures includes a conductive tap structure protruding through the corresponding trench insulating layer. An interlayer dielectric material is above the trench insulating layers and the gate insulating layers. A conductive structure is in direct contact with the conductive tap structure of the one of the plurality of conductive trench contact structures.

公开(公告)号：US20200066629A1

公开(公告)日：2020-02-27

申请号：US16346873

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Richard E. SCHENKER ,  Robert L. BRISTOL ,  Kevin L. LIN ,  Florian GSTREIN ,  James M. BLACKWELL ,  Marie KRYSAK ,  Manish CHANDHOK ,  Paul A. NYHUS ,  Charles H. WALLACE ,  Curtis W. WARD ,  Swaminathan SIVAKUMAR ,  Elliot N. TAN

IPC: H01L23/528 ,  H01L27/088 ,  H01L23/532 ,  H01L29/78 ,  H01L23/522

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

公开(公告)号：US20200066521A1

公开(公告)日：2020-02-27

申请号：US16489331

申请日：2017-03-31

Applicant: INTEL CORPORATION

Inventor： Kevin LIN ,  Rami HOURANI ,  Elliot N. TAN ,  Manish CHANDHOK ,  Anant H. JAHAGIRDAR ,  Robert L. BRISTOL ,  Richard E. SCHENKER ,  Aaron Douglas LILAK

IPC: H01L21/033 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/32 ,  H01L21/3115

Abstract: A computing device including tight pitch features and a method of fabricating a computing device using colored spacer formation is disclosed. The computing device includes a memory and an integrated circuit coupled to the memory. The integrated circuit includes a first multitude of features above a substrate. The integrated circuit die includes a second multitude of features above the substrate. The first multitude of features and the second multitude of features are same features disposed in a first direction. The first multitude of features interleave with the second multitude of features. The first multitude of features has a first size and the second multitude of features has a second size.

公开(公告)号：US20200058548A1

公开(公告)日：2020-02-20

申请号：US16347507

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Eungnak HAN ,  Rami HOURANI ,  Florian GSTREIN ,  Gurpreet SINGH ,  Scott B. CLENDENNING ,  Kevin L. LIN ,  Manish CHANDHOK

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/033 ,  H01L23/522

Abstract: Selective hardmask-based approaches for conductive via fabrication are described. In an example, an integrated circuit structure includes a plurality of conductive lines in an inter-layer dielectric (ILD) layer above a substrate. The plurality of conductive lines includes alternating non-recessed conductive lines and recessed conductive lines. The non-recessed conductive lines are substantially co-planar with the ILD layer, and the recessed conductive lines are recessed relative to an uppermost surface of the ILD layer. A dielectric capping layer is in recess regions above the recessed conductive lines. A hardmask layer is over the non-recessed conductive lines but not over the dielectric capping layer of the recessed conductive lines. The hardmask layer differs in composition from the dielectric capping layer. A conductive via is in an opening in the dielectric capping layer and on one of the recessed conductive lines. A portion of the conductive via is on a portion of the hardmask layer.

公开(公告)号：US20200006138A1

公开(公告)日：2020-01-02

申请号：US16024692

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Kevin LIN ,  Sudipto NASKAR ,  Manish CHANDHOK ,  Miriam RESHOTKO ,  Rami HOURANI

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

Abstract: Embodiments include an interconnect structure and methods of forming such an interconnect structure. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD) and a first interconnect layer with a plurality of first conductive traces partially embedded in the first ILD. In an embodiment, an etch stop layer is formed over surfaces of the first ILD and sidewall surfaces of the first conductive traces. In an embodiment, the interconnect structure further comprises a second interconnect layer that includes a plurality of second conductive traces. In an embodiment, a via between the first interconnect layer and the second interconnect layer may be self-aligned with the first interconnect layer.