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    Virtual storage services for client computing devices
    11.
    发明授权
    Virtual storage services for client computing devices 有权

    公开(公告)号：US11615194B2

    公开(公告)日：2023-03-28

    申请号：US16975661

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： Changzheng Wei ,  Ziye Yang ,  Junyuan Wang ,  Cunming Liang ,  Junhua Hou ,  Weigang Li ,  Ping Yu ,  Yi Yang ,  Baoqian Li ,  Xin Zeng

    IPC: G06F21/60 ,  G06F16/14 ,  H04L9/08 ,  H04L9/40 ,  H04L67/1097

    Abstract: Embodiments include apparatuses, methods, and systems including one or more servers and one or more storage devices, coupled with each other, to provide virtual storage service to store a file and meta data of the file for a client computing device. The file and the meta data of the file may be encrypted by the client computing device before providing to the virtual storage service. The file may be encrypted with a secret key of the client computing device, and the meta data of the file may be encrypted with a shared session key between the client computing device and the virtual storage service. The encrypted file may be stored in the one or more storage devices, and the encrypted meta data of the file may be stored in one or more secured areas of the one or more servers. Other embodiments may also be described and claimed.

    Technologies for hybrid field-programmable gate array application-specific integrated circuit code acceleration
    12.
    发明授权
    Technologies for hybrid field-programmable gate array application-specific integrated circuit code acceleration 有权

    公开(公告)号：US11372684B2

    公开(公告)日：2022-06-28

    申请号：US17220763

    申请日：2021-04-01

    Applicant: Intel Corporation

    Inventor： Ned M. Smith ,  Changzheng Wei ,  Songwu Shen ,  Ziye Yang ,  Junyuan Wang ,  Weigang Li ,  Wenqian Yu

    IPC: G06F9/50 ,  G06F21/76 ,  G06F21/60

    Abstract: Technologies for hybrid acceleration of code include a computing device (100) having a processor (120), a field-programmable gate array (FPGA) (130), and an application-specific integrated circuit (ASIC) (132). The computing device (100) offloads a service request, such as a cryptographic request or a packet processing request, to the FPGA (130). The FPGA (130) performs one or more algorithmic tasks of an algorithm to perform the service request. The FPGA (130) determines one or more primitive tasks associated with an algorithm task and encapsulates each primitive task in a buffer that is accessible by the ASIC (132). The ASIC (132) performs the primitive tasks in response to encapsulation in the buffer, and the FPGA (130) returns results of the algorithm. The primitive operations may include cryptographic primitives such as modular exponentiation, modular multiplicative inverse, and modular multiplication. The results may be returned to the processor (120) or a network interface controller of the computing device (100).

    TECHNOLOGIES FOR CACHE SIDE CHANNEL ATTACK DETECTION AND MITIGATION
    14.
    发明申请
    TECHNOLOGIES FOR CACHE SIDE CHANNEL ATTACK DETECTION AND MITIGATION 审中-公开

    公开(公告)号：US20190042739A1

    公开(公告)日：2019-02-07

    申请号：US16022976

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： John J. Browne ,  Marcel Cornu ,  Timothy Verrall ,  Tomasz Kantecki ,  Niall Power ,  Weigang Li ,  Eoin Walsh ,  Maryam Tahhan

    IPC: G06F21/55 ,  G06F21/56

    Abstract: Technologies for cache side channel attack detection and mitigation include an analytics server and one or more monitored computing devices. The analytics server polls each computing device for analytics counter data. The computing device generates the analytics counter data using a resource manager of a processor of the computing device. The analytics counter data may include last-level cache data or memory bandwidth data. The analytics server identifies suspicious core activity based on the analytics counter data and, if identified, deploys a detection process to the computing device. The computing device executes the detection process to identify suspicious application activity. If identified, the computing device may perform one or more corrective actions. Corrective actions include limiting resource usage by a suspicious process using the resource manager of the processor. The resource manager may limit cache occupancy or memory bandwidth used by the suspicious process. Other embodiments are described and claimed.

    DEVICE, SYSTEM, AND METHOD FOR INSPECTING DIRECT MEMORY ACCESS REQUESTS
    15.
    发明公开
    DEVICE, SYSTEM, AND METHOD FOR INSPECTING DIRECT MEMORY ACCESS REQUESTS 审中-公开

    公开(公告)号：US20230418773A1

    公开(公告)日：2023-12-28

    申请号：US18035705

    申请日：2020-12-24

    Applicant: Intel Corporation

    Inventor： Kaijie Guo ,  Xin Zeng ,  Ned Smith ,  Weigang Li ,  Junyuan Wang ,  Songwu Shen ,  Zijuan Fan ,  Yao Huo ,  Maksim Lukoshkov ,  Laurent Coquerel

    IPC: G06F13/28

    CPC classification number: G06F13/28

    Abstract: Techniques and mechanisms for determining an operation to be performed with a direct memory access (DMA) request. An inspection unit (105) is coupled between an input-output memory management unit (IOMMU) (120) and an endpoint device (118). The inspection unit (105) stores a registry (330) comprising entries (332) which each correspond to a respective address, and a respective one or more resources of the endpoint device (118). A given entry (332) of the registry (330) is created based on a message from the IOM MU (120) which indicates the successful completion of an address translation to facilitate a DMA request. The endpoint device (118) performs a search, based on a DMA request, to determine if any registry (330) entry (332) indicates a combination of an address and an endpoint resource, where said combination matches a corresponding combination indicated by the DMA request. Communication of the DMA request to the IOMMU (120) is contingent on a result of the search.

    Technologies for internet of things key management
    17.
    发明授权
    Technologies for internet of things key management 有权

    公开(公告)号：US11115193B2

    公开(公告)日：2021-09-07

    申请号：US16649192

    申请日：2017-12-29

    Applicant: INTEL CORPORATION

    Inventor： Changzheng Wei ,  Junyuan Wang ,  Ned Smith ,  Weigang Li ,  Ping Yu

    IPC: H04L9/08 ,  G16Y30/10 ,  H04L9/32 ,  G06F21/45 ,  H04L29/06

    Abstract: Technologies for key management of internet-of-things (IoT) devices include an IoT device, an authority center server, and a group management server. The IoT device is configured to authenticate with an authority center server via an offline communication channel, receive a group member private key as a function of the authentication with the authority center server, and authenticate with a group management server via a secure online communication channel using the group member private key. The IoT device is further configured to receive a group shared key as a function of the authentication with the group management server, encrypt secret data with the group shared key, and transmit the encrypted secret data to the group management server. Other embodiments are described herein.

    Technologies for cache side channel attack detection and mitigation
    19.
    发明授权
    Technologies for cache side channel attack detection and mitigation 有权

    公开(公告)号：US10860714B2

    公开(公告)日：2020-12-08

    申请号：US16022976

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： John J. Browne ,  Marcel Cornu ,  Timothy Verrall ,  Tomasz Kantecki ,  Niall Power ,  Weigang Li ,  Eoin Walsh ,  Maryam Tahhan

    IPC: G06F21/55 ,  G06F21/56

    Abstract: Technologies for cache side channel attack detection and mitigation include an analytics server and one or more monitored computing devices. The analytics server polls each computing device for analytics counter data. The computing device generates the analytics counter data using a resource manager of a processor of the computing device. The analytics counter data may include last-level cache data or memory bandwidth data. The analytics server identifies suspicious core activity based on the analytics counter data and, if identified, deploys a detection process to the computing device. The computing device executes the detection process to identify suspicious application activity. If identified, the computing device may perform one or more corrective actions. Corrective actions include limiting resource usage by a suspicious process using the resource manager of the processor. The resource manager may limit cache occupancy or memory bandwidth used by the suspicious process. Other embodiments are described and claimed.

    SCALABLE AND SECURE RESOURCE ISOLATION AND SHARING FOR IoT NETWORKS
    20.
    发明申请
    SCALABLE AND SECURE RESOURCE ISOLATION AND SHARING FOR IoT NETWORKS 审中-公开

    公开(公告)号：US20190014117A1

    公开(公告)日：2019-01-10

    申请号：US15865984

    申请日：2018-01-09

    Applicant: Intel Corporation

    Inventor： Weigang Li ,  Ned M. Smith ,  Changzheng Wei

    IPC: H04L29/06 ,  H04L29/08 ,  H04L9/32

    Abstract: Various systems and methods of scalable and secure resource isolation and sharing for Internet of Things (IoT) networks, are described. Techniques for requesting inter-domain resource access and enabling resource sharing with use of an inter domain token are also described. In an example, communications in an IoT network to establish connectivity between a first device in a first domain and a second device in a second domain may include: receiving, from the first device at a collaboration cloud service, a request to access a resource of the second device; requesting and receiving, from an authorization provider, an inter-domain authorization token; and requesting, from the second device, access to the resource using the inter-domain authorization token; communications from the first device to access the second device are then performed between the first device and the second device based on a session key obtained with the inter-domain authorization token.

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