公开(公告)号：US20240388018A1

公开(公告)日：2024-11-21

申请号：US18199269

申请日：2023-05-18

Applicant: Intel Corporation

Inventor： Karumbu MEYYAPPAN ,  Gregorio R. MURTAGIAN ,  Ziyin LIN

IPC: H01R12/52 ,  H01L23/498 ,  H01R3/08 ,  H05K1/18 ,  H05K3/32

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate with a first surface and a second surface opposite from the first surface. In an embodiment, pads are on the first surface of the package substrate, where the pads have a first width. In an embodiment, a layer is on the first surface of the package substrate, where the layer comprises wells through the layer, and where the wells have a second width that is wider than the first width. In an embodiment, a liquid metal is in the wells and in contact with the pads.

公开(公告)号：US20240363520A1

公开(公告)日：2024-10-31

申请号：US18139083

申请日：2023-04-25

Applicant: Intel Corporation

Inventor： Ziyin LIN ,  Boer LIU ,  Dingying David XU ,  Karumbu MEYYAPPAN

IPC: H01L23/498 ,  H01R12/52

CPC classification number: H01L23/49894 ,  H01L23/49811 ,  H01L23/49833 ,  H01R12/52 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01R4/2406 ,  H01R12/58 ,  H05K1/181 ,  H05K2201/10189 ,  H05K2201/10378

Abstract: Embodiments disclosed herein include a package substrate. In an embodiment, the package substrate comprises a substrate with a layer on the substrate. In an embodiment, the layer comprises a plurality of wells. In an embodiment, a liquid metal is in the plurality of wells. In an embodiment, a cap is on the layer to seal the plurality of wells, where the cap comprises a polymer, and fibers within the polymer.

公开(公告)号：US20240213164A1

公开(公告)日：2024-06-27

申请号：US18089483

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Minglu LIU ,  Gang DUAN ,  Liang HE ,  Ziyin LIN ,  Elizabeth NOFEN ,  Yiqun BAI ,  Jonathan ATKINS ,  Jesus S. NIETO PESCADOR ,  Srinivas V. PIETAMBARAM ,  Kristof DARMAWIKARTA

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5381 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/14 ,  H01L2224/16104

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate, and an opening in the package substrate. In an embodiment, a plurality of first pads are provided at a bottom of the opening, and a bridge die is in the opening. In an embodiment, the bridge die comprises a plurality of second pads that are coupled to the first pads by solder. In an embodiment, a non-conductive film (NCF) is around the solder between the first pads and the second pads.

公开(公告)号：US20240071848A1

公开(公告)日：2024-02-29

申请号：US17895916

申请日：2022-08-25

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Haobo CHEN ,  Brandon C. MARIN ,  Srinivas V. PIETAMBARAM ,  Bai NIE ,  Gang DUAN ,  Kyle ARRINGTON ,  Ziyin LIN ,  Hongxia FENG ,  Yiqun BAI ,  Xiaoying GUO ,  Dingying David XU ,  Jeremy D. ECTON ,  Kristof DARMAWIKARTA ,  Suddhasattwa NAD

IPC: H01L23/15 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/15 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827

Abstract: Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a core, where the core comprises glass. In an embodiment, a first layer is under the core, a second layer is over the core, and a via is through the core, the first layer, and the second layer. In an embodiment a width of the via through the core is equal to a width of the via through the first layer and the second layer. In an embodiment, the package substrate further comprises a first pad under the via, and a second pad over the via.

公开(公告)号：US20220196937A1

公开(公告)日：2022-06-23

申请号：US17132851

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Bassam ZIADEH ,  Jingyi HUANG ,  Yiqun BAI ,  Ziyin LIN ,  Vipul MEHTA ,  Joseph VAN NAUSDLE

IPC: G02B6/42

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to hydrophobic features to block or slow the spread of epoxy. These hydrophobic features are placed either on a die surface or on a substrate surface to control epoxy spread between the die in the substrate to prevent formation of fillets. Packages with these hydrophobic features may include a substrate, a die with a first side and a second side opposite the first side, the second side of the die physically coupled with a surface of the substrate, and a hydrophobic feature coupled with the second side of the die or the surface of the substrate to reduce a flow of epoxy on the substrate or die. In embodiments, these hydrophobic features may include a chemical barrier or a laser ablated area on the substrate or die. Other embodiments may be described and/or claimed.

公开(公告)号：US20210242102A1

公开(公告)日：2021-08-05

申请号：US16781894

申请日：2020-02-04

Applicant: Intel Corporation

Inventor： Elizabeth NOFEN ,  Ziyin LIN ,  Nisha ANANTHAKRISHNAN

IPC: H01L23/31 ,  H05K1/18 ,  C08L63/00 ,  C08L75/04 ,  C08L67/00 ,  C08L83/04 ,  C08K5/3432 ,  C08K3/36 ,  C08K3/22 ,  C08K3/38 ,  H01L23/50

Abstract: Embodiments herein describe techniques for an IC package including an electronic component, and an underfill material around or below the electronic component to support the electronic component. The underfill material includes a resin and a thermolatent onium salt as a cationic cure for the underfill material. The thermolatent onium salt comprises an organic cation with a heteroatom center, and an anion including metalloid fluoride. The heteroatom center includes an iodonium, sulphonium, phosphonium, or N-containing onium. Other embodiments may be described and/or claimed.