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    MoOx-Based Resistance Switching Materials
    11.
    发明申请
    MoOx-Based Resistance Switching Materials 有权
    基于MoOx的电阻开关材料

    公开(公告)号：US20140183432A1

    公开(公告)日：2014-07-03

    申请号：US13727958

    申请日：2012-12-27

    Applicant: INTERMOLECULAR, INC.

    Inventor： Sergey Barabash ,  Tony P. Chiang ,  Dipankar Pramanik

    IPC: H01L45/00

    CPC classification number: H01L45/145 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1641

    Abstract: Molybdenum oxide can be used to form switching elements in a resistive memory device. The atomic ratio of oxygen to molybdenum can be between 2 and 3. The molybdenum oxide exists in various Magneli phases, such as Mo13O33, Mo4O11, Mo17O47, Mo8O23, or Mo9O26. An electric field can be established across the switching layers, for example, by applying a set or reset voltage. The electric field can cause movement of the oxygen charges, e.g., O2− ions, changing the composition profile of the switching layers, forming bistable states, including a high resistance state with MoO3 and a low resistance state with MoOx (x

    Abstract translation: 氧化钼可用于在电阻式存储器件中形成开关元件。 氧与钼的原子比可以在2和3之间。氧化钼存在于各种Magneli相中，例如Mo13O33，Mo4O11，Mo17O47，Mo8O23或Mo9O26。 可以跨开关层建立电场，例如通过施加置位或复位电压。 电场可导致氧电荷的移动，例如O 2离子，改变开关层的组成分布，形成双稳态，包括具有MoO 3的高电阻状态和具有MoO x（x <3）的低电阻状态）。

    Methods of Manufacturing Embedded Bipolar Switching Resistive Memory
    13.
    发明申请
    Methods of Manufacturing Embedded Bipolar Switching Resistive Memory 有权
    嵌入式双极开关电阻式存储器的制造方法

    公开(公告)号：US20140169062A1

    公开(公告)日：2014-06-19

    申请号：US13714173

    申请日：2012-12-13

    Applicant: INTERMOLECULAR, INC.

    Inventor： Mankoo Lee ,  Tony Chiang ,  Dipankar Pramanik

    IPC: G11C13/00

    CPC classification number: G11C13/0033 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2213/72 ,  G11C2213/76 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2454 ,  H01L29/785 ,  H01L29/868 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

    Abstract: Non linear current response circuits can be used in embedded resistive memory cell for reducing power consumption, together with improving reliability of the memory array. The non linear current response circuits can include two back to back leaky PIN diodes, two parallel anti-directional PIN diodes, two back to back Zener-type metal oxide diodes, or ovonic switching elements, along with current limiting resistor for standby power reduction at the low voltage region. Also, the proposed embedded ReRAM implementation methods based upon 1T2D1R scheme can be integrated into the advanced FEOL process technologies including vertical pillar transistor and/or 3D fin-shaped field effect transistor (FinFET) for realizing a highly compact cell density.

    Abstract translation: 非线性电流响应电路可用于嵌入式电阻式存储单元，以降低功耗，同时提高存储器阵列的可靠性。 非线性电流响应电路可以包括两个背靠背泄漏的PIN二极管，两个并联的反向PIN二极管，两个背靠背的齐纳二极型金属氧化物二极管或者二极管开关元件，以及用于待机功率降低的限流电阻 低电压区域。 此外，所提出的基于1T2D1R方案的嵌入式ReRAM实现方法可以集成到先进的FEOL工艺技术中，包括用于实现高度紧凑的单元密度的立柱晶体管和/或3D鳍状场效应晶体管（FinFET）。

    Controlling ReRam Forming Voltage with Doping
    14.
    发明申请
    Controlling ReRam Forming Voltage with Doping 有权
    用掺杂控制ReRam成型电压

    公开(公告)号：US20140166958A1

    公开(公告)日：2014-06-19

    申请号：US13719051

    申请日：2012-12-18

    Applicant: INTERMOLECULAR, INC.

    Inventor： Sergey Barabash ,  Charlene Chen ,  Dipankar Pramanik

    IPC: H01L45/00

    CPC classification number: H01L45/1616 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1641

    Abstract: An internal electrical field in a resistive memory element can be formed to reduce the forming voltage. The internal electric field can be formed by incorporating one or more charged layers within the switching dielectric layer of the resistive memory element. The charged layers can include adjacent charge layers to form dipole layers. The charged layers can be formed at or near the interface of the switching dielectric layer with an electrode layer. Further, the charged layer can be oriented with lower valence substitution side towards lower work function electrode, and higher valence substitution side towards higher work function electrode.

    Abstract translation: 可以形成电阻式存储元件中的内部电场以降低成形电压。 可以通过在电阻式存储元件的开关电介质层内并入一个或多个带电层来形成内部电场。 带电层可以包括相邻的电荷层以形成偶极层。 带电层可以在开关电介质层的界面处或附近形成电极层。 此外，带电层可以朝向较低功函电极的较低价取代面取向，而朝较高功函电极取向较高的取代价。

    Memory device having an integrated two-terminal current limiting resistor
    15.
    发明授权
    Memory device having an integrated two-terminal current limiting resistor 有权
    存储器件具有集成的两端限流电阻

    公开(公告)号：US08748237B2

    公开(公告)日：2014-06-10

    申请号：US14064787

    申请日：2013-10-28

    Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

    Inventor： Dipankar Pramanik ,  Tony P. Chiang ,  Mankoo Lee

    IPC: H01L29/8605

    CPC classification number: H01L45/14 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/76 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16

    Abstract: A resistor structure incorporated into a resistive switching memory cell or device to form memory devices with improved device performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory device. A method is also provided for making such memory device. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory device, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory device. The incorporation of the resistor structure is very useful in obtaining desirable levels of device switching currents that meet the switching specification of various types of memory devices. The memory devices may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.

    Abstract translation: 提供了并入电阻式开关存储单元或装置中以形成具有改进的器件性能和寿命的存储器件的电阻器结构。 电阻器结构可以是设计成减小流过存储器件的最大电流的两端结构。 还提供了一种用于制造这种存储器件的方法。 该方法包括沉积电阻器结构并沉积存储器件的电阻式开关存储单元的可变电阻层，其中电阻器结构与可变电阻层串联设置以限制存储器件的开关电流。 电阻器结构的结合对于获得满足各种类型的存储器件的开关规范的期望的器件开关电流水平是非常有用的。 存储器件可以形成为可用于各种电子器件的大容量非易失性存储器集成电路的一部分。

    Atomic Layer Deposition of Hafnium and Zirconium Oxides for Memory Applications
    17.
    发明申请
    Atomic Layer Deposition of Hafnium and Zirconium Oxides for Memory Applications 审中-公开
    用于记忆应用的铪和氧化锆的原子层沉积

    公开(公告)号：US20130334484A1

    公开(公告)日：2013-12-19

    申请号：US13972587

    申请日：2013-08-21

    Applicant: Intermolecular Inc. ,  SanDisk 3D LLC ,  Kabushiki Kaisha Toshiba

    Inventor： Yun Wang ,  Tony P. Chiang ,  Vidyut Gopal ,  Imran Hashim ,  Dipankar Pramanik

    IPC: H01L45/00

    CPC classification number: H01L45/146 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1616

    Abstract: Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack having a metal oxide buffer layer disposed on or over a metal oxide bulk layer. The metal oxide bulk layer contains a metal-rich oxide material and the metal oxide buffer layer contains a metal-poor oxide material. The metal oxide bulk layer is less electrically resistive than the metal oxide buffer layer since the metal oxide bulk layer is less oxidized or more metallic than the metal oxide buffer layer. In one example, the metal oxide bulk layer contains a metal-rich hafnium oxide material and the metal oxide buffer layer contains a metal-poor zirconium oxide material.

    Abstract translation: 本发明的实施例一般涉及用于制造这种存储器件的非易失性存储器件和方法。 用于形成改进的存储器件（例如ReRAM单元）的方法提供优化的原子层沉积（ALD）工艺，用于形成金属氧化物膜堆叠，其具有设置在金属氧化物本体层上或其上的金属氧化物缓冲层。 金属氧化物本体层含有富金属氧化物材料，金属氧化物缓冲层含有贫金属氧化物。 由于金属氧化物本体层比金属氧化物缓冲层氧化较少或更金属，所以金属氧化物本体层的电阻小于金属氧化物缓冲层的电阻。 在一个实例中，金属氧化物本体层含有富金属氧化铪材料，金属氧化物缓冲层含有贫金属氧化锆材料。

    Memory Cell Having an Integrated Two-Terminal Current Limiting Resistor
    18.
    发明申请
    Memory Cell Having an Integrated Two-Terminal Current Limiting Resistor 有权
    具有集成两端限流电阻的存储单元

    公开(公告)号：US20130221315A1

    公开(公告)日：2013-08-29

    申请号：US13721310

    申请日：2012-12-20

    Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

    Inventor： Yun Wang ,  Tony P. Chiang ,  Imran Hashim ,  Tim Minvielle ,  Dipankar Pramanik ,  Takeshi Yamaguchi

    IPC: H01L45/00

    CPC classification number: H01L45/12 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

    Abstract: A resistor structure incorporated into a resistive switching memory cell with improved performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory cell. A method is also provided for making such a memory cell. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory cell, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory cell. The incorporation of the resistor structure is very useful in obtaining desirable levels of switching currents that meet the switching specification of various types of memory cells. The memory cells may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.

    Abstract translation: 提供了一种结合到具有改进的性能和寿命的电阻式开关存储单元中的电阻器结构。 电阻器结构可以是设计成减小流过存储器单元的最大电流的两端结构。 还提供了一种用于制造这种存储单元的方法。 该方法包括沉积电阻器结构并沉积存储单元的电阻式开关存储单元的可变电阻层，其中电阻器结构与可变电阻层串联布置以限制存储单元的开关电流。 电阻器结构的结合对于获得满足各种类型的存储器单元的开关规范的期望的开关电流水平是非常有用的。 存储单元可以形成为可用于各种电子设备的大容量非易失性存储器集成电路的一部分。

    Superconducting circuits with reduced microwave absorption
    20.
    发明授权
    Superconducting circuits with reduced microwave absorption 有权
    具有减少微波吸收的超导电路

    公开(公告)号：US09455073B2

    公开(公告)日：2016-09-27

    申请号：US14259455

    申请日：2014-04-23

    Applicant: Intermolecular, Inc. ,  Northrop Grumman Systems Corporation

    Inventor： Sergey Barabash ,  Dipankar Pramanik ,  Andrew Steinbach ,  Chris Kirby

    IPC: H01B12/02 ,  H01L39/24 ,  H01L39/22

    CPC classification number: H01B12/02 ,  H01L39/22 ,  H01L39/24 ,  Y10S505/704 ,  Y10S505/706

    Abstract: Provided are superconducting circuits, methods of operating these superconducting circuits, and methods of determining processing conditions for operating these superconducting circuits. A superconducting circuit includes a superconducting element, a conducting element, and a dielectric element disposed between the superconducting element and the conducting element. The conducting element may be another superconducting element, a resonating element, or a conducting casing. During operation of the superconducting element a direct current (DC) voltage is applied between the superconducting element and the conducting element. This application of the DC voltage reduces average microwave absorption of the dielectric element. In some embodiments, when the DC voltage is first applied, the microwave absorption may initially rise and then fall below the no-voltage absorption level. The DC voltage level may be determined by testing the superconducting circuit at different DC voltage levels and selecting the one with the lowest microwave absorption.

    Abstract translation: 提供超导电路，操作这些超导电路的方法以及确定用于操作这些超导电路的处理条件的方法。 超导电路包括超导元件，导电元件和设置在超导元件和导电元件之间的介电元件。 导电元件可以是另一种超导元件，谐振元件或导电壳体。 在超导元件的操作期间，在超导元件和导电元件之间施加直流（DC）电压。 DC电压的这种应用降低了介电元件的平均微波吸收。 在一些实施例中，当首先施加DC电压时，微波吸收可以最初升高然后降低到无电压吸收水平以下。 直流电压电平可以通过在不同的直流电压电平下测试超导电路并选择具有最低微波吸收的电路来确定。

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