公开(公告)号：US20150064873A1

公开(公告)日：2015-03-05

申请号：US14527276

申请日：2014-10-29

Applicant: Intermolecular, Inc.

Inventor： Sergey Barabash ,  Charlene Chen ,  Dipankar Pramanik

IPC: H01L45/00

CPC classification number: H01L45/1616 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1641

Abstract: An internal electrical field in a resistive memory element can be formed to reduce the forming voltage. The internal electric field can be formed by incorporating one or more charged layers within the switching dielectric layer of the resistive memory element. The charged layers can include adjacent charge layers to form dipole layers. The charged layers can be formed at or near the interface of the switching dielectric layer with an electrode layer. Further, the charged layer can be oriented with lower valence substitution side towards lower work function electrode, and higher valence substitution side towards higher work function electrode.

Abstract translation: 可以形成电阻式存储元件中的内部电场以降低成形电压。 可以通过在电阻式存储元件的开关电介质层内并入一个或多个带电层来形成内部电场。 带电层可以包括相邻的电荷层以形成偶极层。 带电层可以在开关电介质层的界面处或附近形成电极层。 此外，带电层可以朝向较低功函电极的较低价取代面取向，而朝较高功函电极取向较高的取代价。

公开(公告)号：US09012260B2

公开(公告)日：2015-04-21

申请号：US14527276

申请日：2014-10-29

Applicant: Intermolecular, Inc.

Inventor： Sergey Barabash ,  Charlene Chen ,  Dipankar Pramanik

IPC: H01L29/82 ,  H01L45/00

CPC classification number: H01L45/1616 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1641

Abstract: An internal electrical field in a resistive memory element can be formed to reduce the forming voltage. The internal electric field can be formed by incorporating one or more charged layers within the switching dielectric layer of the resistive memory element. The charged layers can include adjacent charge layers to form dipole layers. The charged layers can be formed at or near the interface of the switching dielectric layer with an electrode layer. Further, the charged layer can be oriented with lower valence substitution side towards lower work function electrode, and higher valence substitution side towards higher work function electrode.

Abstract translation: 可以形成电阻式存储元件中的内部电场以降低成形电压。 可以通过在电阻式存储元件的开关电介质层内并入一个或多个带电层来形成内部电场。 带电层可以包括相邻的电荷层以形成偶极层。 带电层可以在开关电介质层的界面处或附近形成电极层。 此外，带电层可以朝向较低功函电极的较低价取代面取向，而朝较高功函电极取向较高的取代价。

公开(公告)号：US20150079727A1

公开(公告)日：2015-03-19

申请号：US14029713

申请日：2013-09-17

Applicant: Intermolecular, Inc.

Inventor： Mankoo Lee ,  Charlene Chen ,  Tony P. Chiang ,  Dipankar Pramanik

IPC: H01L29/66

CPC classification number: H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78693

Abstract: Embodiments described herein provide improvements to indium-gallium-zinc oxide devices, such as amorphous IGZO thin film transistors, and methods for forming such devices. A relatively thin a-IGZO channel may be utilized. A plasma treatment chemical precursor passivation may be provided to the front-side a-IGZO interface. High-k dielectric materials may be used in the etch-stop layer at the back-side a-IGZO interface. A barrier layer may be formed above the gate electrode before the gate dielectric layer is deposited. The conventional etch-stop layer, typically formed before the source and drain regions are defined, may be replaced by a pre-passivation layer that is formed after the source and drain regions are defined and may include multiple sub-layers.

Abstract translation: 本文描述的实施例提供了诸如非晶IGZO薄膜晶体管的铟镓镓氧化物器件的改进以及用于形成这种器件的方法。 可以使用相对薄的a-IGZO通道。 可以向前侧a-IGZO界面提供等离子体处理化学前体钝化。 高k电介质材料可用于背面a-IGZO界面的蚀刻停止层。 在栅介质层沉积之前，可以在栅电极上方形成阻挡层。 通常在源极和漏极区域之前形成的常规蚀刻停止层可以由在源极和漏极区域之间形成并且可以包括多个子层形成的预钝化层来代替。

公开(公告)号：US20140264224A1

公开(公告)日：2014-09-18

申请号：US13969469

申请日：2013-08-16

Applicant: Intermolecular, Inc.

Inventor： Xuena Zhang ,  Sergey Barabash ,  Charlene Chen ,  Dipankar Pramanik

IPC: H01L45/00

CPC classification number: H01L27/2418 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/15 ,  G11C2213/71 ,  G11C2213/77 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/283 ,  H01L21/324 ,  H01L22/12 ,  H01L22/34 ,  H01L27/24 ,  H01L27/2463 ,  H01L28/60 ,  H01L45/00 ,  H01L45/04 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/14 ,  H01L45/144 ,  H01L45/145 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1641 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Resistive random access memory (ReRAM) cells can include an embedded metal nanoparticle switching layer and electrodes. The metal nanoparticles can be formed using a micelle solution. The generation of the nanoparticles can be controlled in multiple dimensions to achieve desirable performance characteristics, such as low power consumption as well as low and consistent switching currents.

Abstract translation: 电阻随机存取存储器（ReRAM）单元可以包括嵌入金属纳米颗粒切换层和电极。 可以使用胶束溶液形成金属纳米颗粒。 可以在多个维度上控制纳米颗粒的产生以实现期望的性能特征，例如低功耗以及低和一致的开关电流。

公开(公告)号：US20130122614A1

公开(公告)日：2013-05-16

申请号：US13713421

申请日：2012-12-13

Applicant: Intermolecular, Inc.

Inventor： Charlene Chen ,  Tony P. Chiang ,  Chi-I Lang ,  Yun Wang

IPC: H01L21/66 ,  G01N21/59

CPC classification number: H01L22/20 ,  G01N21/59 ,  H01L21/02491 ,  H01L21/02527 ,  H01L21/0262 ,  H01L22/12 ,  H01L29/1606

Abstract: A method and system includes a first substrate and a second substrate, each substrate comprising a predetermined baseline transmittance value at a predetermine wavelength of light, processing regions on the first substrate by combinatorially varying at least one of materials, process conditions, unit processes, and process sequences associated with the graphene production, performing a first characterization test on the processed regions on the first substrate to generate first results, processing regions on a second substrate in a combinatorial manner by varying at least one of materials, process conditions, unit processes, and process sequences associated with the graphene production based on the first results of the first characterization test, performing a second characterization test on the processed regions on the second substrate to generate second results, and determining whether at least one of the first substrate and the second substrate meet a predetermined quality threshold based on the second results.

Abstract translation: 一种方法和系统包括第一衬底和第二衬底，每个衬底在光的预定波长处包括预定的基线透射率值，第一衬底上的处理区域通过组合地改变材料，工艺条件，单元工艺中的至少一个和 与所述石墨烯生产相关联的工艺序列，对所述第一衬底上的所述经处理区域执行第一表征测试以产生第一结果，通过改变材料，工艺条件，单位过程中的至少一种以组合方式处理第二衬底上的区域， 以及基于第一表征测试的第一结果与石墨烯生产相关联的处理顺序，对第二衬底上的经处理区域执行第二表征测试以产生第二结果，以及确定第一衬底和第二衬底中的至少一个 基板满足预定的质量阈值 基于第二个结果。

公开(公告)号：US08907313B2

公开(公告)日：2014-12-09

申请号：US13719051

申请日：2012-12-18

Applicant: Intermolecular, Inc.

Inventor： Sergey Barabash ,  Charlene Chen ,  Dipankar Pramanik

IPC: H01L29/02 ,  H01L45/00

CPC classification number: H01L45/1616 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1641

Abstract: An internal electrical field in a resistive memory element can be formed to reduce the forming voltage. The internal electric field can be formed by incorporating one or more charged layers within the switching dielectric layer of the resistive memory element. The charged layers can include adjacent charge layers to form dipole layers. The charged layers can be formed at or near the interface of the switching dielectric layer with an electrode layer. Further, the charged layer can be oriented with lower valence substitution side towards lower work function electrode, and higher valence substitution side towards higher work function electrode.

Abstract translation: 可以形成电阻式存储元件中的内部电场以降低成形电压。 可以通过在电阻式存储元件的开关电介质层内并入一个或多个带电层来形成内部电场。 带电层可以包括相邻的电荷层以形成偶极层。 带电层可以在开关电介质层的界面处或附近形成电极层。 此外，带电层可以朝向较低功函电极的较低价取代面取向，而朝较高功函电极取向较高的取代价。

公开(公告)号：US20170104031A1

公开(公告)日：2017-04-13

申请号：US15287091

申请日：2016-10-06

Applicant: Intermolecular, Inc.

Inventor： Mark Clark ,  Prashant Phatak ,  Charlene Chen ,  Ashish Bodke ,  Salil Mujumdar ,  Federico Nardi ,  Satbir Kahlon ,  Sergey V. Barabash ,  Feihu Wang

IPC: H01L27/24 ,  G11C11/16 ,  G11C13/00 ,  H01L45/00 ,  H01L27/22

CPC classification number: G11C11/1659 ,  G11C13/003 ,  G11C2213/53 ,  G11C2213/72 ,  G11C2213/76 ,  H01L27/224 ,  H01L27/2409 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/143 ,  H01L45/144

Abstract: Provided are selector elements with active components comprising insulating matrices and mobile ions disposed within these insulating matrices. Also provided are methods of operating such selector elements. The insulating matrices and mobile ions may be formed from different combinations of materials. For example, the insulating matrix may comprise amorphous silicon or silicon oxide, while mobile ions may be silver ions. In another example, the active component comprises copper and germanium, selenium, or tellerium, e.g., Se61Cu39, Se67Cu33, or Se56Cu44. The active component may be a multilayered structure with a variable composition throughout the structure. For example, the concentration of mobile ions may be higher in a center of the structure, away from the electrode interfaces. In some embodiments, outer layers may be formed from Ge33Se24Cu47, while the middle layer may be formed from Ge47Se29Cu24.

公开(公告)号：US09105563B2

公开(公告)日：2015-08-11

申请号：US13713421

申请日：2012-12-13

Applicant: Intermolecular, Inc.

Inventor： Charlene Chen ,  Tony P. Chiang ,  Chi-I Lang ,  Yun Wang

IPC: G01N21/59 ,  H01L21/66 ,  H01L29/16 ,  H01L21/02

CPC classification number: H01L22/20 ,  G01N21/59 ,  H01L21/02491 ,  H01L21/02527 ,  H01L21/0262 ,  H01L22/12 ,  H01L29/1606

Abstract: A method and system includes a first substrate and a second substrate, each substrate comprising a predetermined baseline transmittance value at a predetermine wavelength of light, processing regions on the first substrate by combinatorially varying at least one of materials, process conditions, unit processes, and process sequences associated with the graphene production, performing a first characterization test on the processed regions on the first substrate to generate first results, processing regions on a second substrate in a combinatorial manner by varying at least one of materials, process conditions, unit processes, and process sequences associated with the graphene production based on the first results of the first characterization test, performing a second characterization test on the processed regions on the second substrate to generate second results, and determining whether at least one of the first substrate and the second substrate meet a predetermined quality threshold based on the second results.

Abstract translation: 一种方法和系统包括第一衬底和第二衬底，每个衬底在光的预定波长处包括预定的基线透射率值，第一衬底上的处理区域通过组合地改变材料，工艺条件，单元工艺中的至少一个和 与所述石墨烯生产相关联的工艺序列，对所述第一衬底上的所述经处理区域执行第一表征测试以产生第一结果，通过改变材料，工艺条件，单位过程中的至少一种以组合方式处理第二衬底上的区域， 以及基于第一表征测试的第一结果与石墨烯生产相关联的处理顺序，对第二衬底上的经处理区域执行第二表征测试以产生第二结果，以及确定第一衬底和第二衬底中的至少一个 基板满足预定的质量阈值 基于第二个结果。

公开(公告)号：US20140264321A1

公开(公告)日：2014-09-18

申请号：US14136000

申请日：2013-12-20

Applicant: Intermolecular, Inc.

Inventor： Haifan Liang ,  Charlene Chen ,  Sang Lee ,  Minh Huu Le ,  Jeroen Van Duren

IPC: H01L27/12 ,  H01L21/02

CPC classification number: H01L21/30604 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/32134 ,  H01L21/465 ,  H01L21/707 ,  H01L27/1225 ,  H01L27/1262 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/7869

Abstract: In some embodiments, oxidants such as ozone (O3) and/or nitrous oxide (N2O) are used during the reactive sputtering of metal-based semiconductor layers used in TFT devices. The O3 and N2O gases are stronger oxidants and result in a decrease in the concentration of oxygen vacancies within the metal-based semiconductor layer. The decrease in the concentration of oxygen vacancies may result in improved stability under conditions of negative bias illumination stress (NBIS).

Abstract translation: 在一些实施方案中，在TFT器件中使用的金属基半导体层的反应溅射期间，使用氧化剂如臭氧（O 3）和/或一氧化二氮（N 2 O）。 O 3和N 2 O气体是更强的氧化剂并且导致金属基半导体层内的氧空位浓度的降低。 氧空位浓度的降低可能导致负偏压照明应力（NBIS）条件下的稳定性提高。

公开(公告)号：US20140166958A1

公开(公告)日：2014-06-19

申请号：US13719051

申请日：2012-12-18

Applicant: INTERMOLECULAR, INC.

Inventor： Sergey Barabash ,  Charlene Chen ,  Dipankar Pramanik

IPC: H01L45/00

CPC classification number: H01L45/1616 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1641

Abstract: An internal electrical field in a resistive memory element can be formed to reduce the forming voltage. The internal electric field can be formed by incorporating one or more charged layers within the switching dielectric layer of the resistive memory element. The charged layers can include adjacent charge layers to form dipole layers. The charged layers can be formed at or near the interface of the switching dielectric layer with an electrode layer. Further, the charged layer can be oriented with lower valence substitution side towards lower work function electrode, and higher valence substitution side towards higher work function electrode.

Abstract translation: 可以形成电阻式存储元件中的内部电场以降低成形电压。 可以通过在电阻式存储元件的开关电介质层内并入一个或多个带电层来形成内部电场。 带电层可以包括相邻的电荷层以形成偶极层。 带电层可以在开关电介质层的界面处或附近形成电极层。 此外，带电层可以朝向较低功函电极的较低价取代面取向，而朝较高功函电极取向较高的取代价。