公开(公告)号：US20150162194A1

公开(公告)日：2015-06-11

申请号：US14102873

申请日：2013-12-11

申请人： STMicroelectronics, Inc. ,  International Business Machines Corporation

发明人： Lawrence A. Clevenger ,  Carl J. Radens ,  Richard S. Wise ,  Yiheng Xu ,  John Zhang

IPC分类号： H01L21/033 ,  H01L21/02 ,  H01L21/306

CPC分类号： H01L21/0337 ,  B81C1/0046 ,  G03F7/0002 ,  H01L21/31144

摘要： Embodiments of present invention provide a method of forming device pattern. The method includes defining a device pattern to be created in a device layer; forming a sacrificial layer on top of the device layer; identifying an imprinting mold that, at a position along a height thereof, has a horizontal cross-sectional shape that represents the device pattern; pushing the imprinting mold uniformly into the sacrificial layer until at least the position of the imprinting mold reaches a level inside the sacrificial layer that is being pushed by the imprinting mold; removing the imprinting mold away from the sacrificial layer; forming a hard mask in recesses created by the imprinting mold in the sacrificial layer, the hard mask has a pattern representing the device pattern; and transferring the pattern of the hard mask into underneath the device layer.

摘要翻译： 本发明的实施例提供一种形成装置图案的方法。 该方法包括定义要在设备层中创建的设备模式; 在器件层的顶部上形成牺牲层; 识别在其高度的位置处具有表示装置图案的水平横截面形状的压印模具; 将压印模均匀地推入牺牲层，直到至少压印模具的位置达到被压印模推送的牺牲层内的水平面; 将所述压印模具远离所述牺牲层移除; 在由牺牲层中的压印模制成的凹部中形成硬掩模，硬掩模具有表示装置图案的图案; 并将硬掩模的图案转移到器件层的下方。

公开(公告)号：US20150140799A1

公开(公告)日：2015-05-21

申请号：US14590238

申请日：2015-01-06

申请人： International Business Machines Corporation

发明人： Kangguo Cheng ,  Ali Khakifirooz ,  Richard S. Wise

IPC分类号： H01L29/66

CPC分类号： H01L29/6656 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7856 ,  H01L29/78606

摘要： A semiconductor device having asymmetric spacers and steps for forming the same are disclosed. The spacers have difference capacitances, with the spacer having a higher capacitance formed over a source region of the device and the spacer having a lower capacitance formed over a drain region of the device. Embodiments of the disclosed invention include spacers made from different materials, having different or substantially equal thicknesses.

摘要翻译： 公开了一种具有不对称间隔物的半导体器件及其形成步骤。 间隔物具有差异电容，间隔物在器件的源极区域上形成较高的电容，并且间隔物在器件的漏极区域上形成较低的电容。 所公开的发明的实施例包括由不同材料制成的间隔物，其具有不同的或基本相等的厚度。

公开(公告)号：US09530665B2

公开(公告)日：2016-12-27

申请号：US14313340

申请日：2014-06-24

申请人： International Business Machines Corporation

发明人： Effendi Leobandung ,  Richard S. Wise

IPC分类号： H01L21/311 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/088 ,  H01L27/12 ,  H01L21/8234

CPC分类号： H01L21/31116 ,  H01L21/31105 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66795

摘要： Forming a field effect transistor device includes forming first and second semiconductor fins on a semiconductor substrate. The first and second semiconductor fins are separated by a trench region. The trench region has a first sidewall corresponding to a sidewall of the first semiconductor fin and a second sidewall corresponding to a sidewall of the second semiconductor fin. A gate stack is arranged over respective channel regions of the first and semiconductor fins. A first sidewall of the gate stack corresponds to a third sidewall of the trench region. A protective layer is formed only on a bottom portion of the trench region and along the first sidewall of the gate stack. The protective layer along the first sidewall of the gate stack defines a gate spacer.

摘要翻译： 形成场效应晶体管器件包括在半导体衬底上形成第一和第二半导体鳍片。 第一和第二半导体散热片被沟槽区分开。 沟槽区域具有对应于第一半导体鳍片的侧壁的第一侧壁和对应于第二半导体鳍片的侧壁的第二侧壁。 栅极堆叠被布置在第一和半导体鳍片的相应沟道区域上。 栅堆叠的第一侧壁对应于沟槽区域的第三侧壁。 仅在沟槽区域的底部和栅极叠层的第一侧壁上形成保护层。 沿着栅极堆叠的第一侧壁的保护层限定栅极间隔物。

公开(公告)号：US09412654B1

公开(公告)日：2016-08-09

申请号：US14697056

申请日：2015-04-27

申请人： International Business Machines Corporation

发明人： Junjing Bao ,  Lawrence A. Clevenger ,  Vincent J. McGahay ,  Joyeeta Nag ,  Richard S. Wise ,  Yiheng Xu

IPC分类号： H01L21/4763 ,  H01L21/44 ,  H01L21/768

CPC分类号： H01L21/76876 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76873

摘要： After forming a copper seed layer on a diffusion barrier layer present on sidewalls and a bottom surface of at least one opening, a graphene sacrificial layer is deposited over the copper seed layer before the copper seed layer is exposed to an environment that oxidizes the copper seed layer, thus providing process flexibility for longer queue times (Q-times) between copper seed layer deposition and copper plating. Next, the graphene sacrificial layer is subjected to a plasma treatment to introduce disorders and defects into the graphene sacrificial layer for removal just before the copper plating. The entire structure is then immersed in a copper plating solution. The copper plating solution dissolves the plasma treated graphene sacrificial layer and forms a copper-containing layer on the re-exposed copper seed layer.

摘要翻译： 在存在于至少一个开口的侧壁和底表面上的扩散阻挡层上形成铜籽晶层之后，在铜籽晶层暴露于氧化铜晶种的环境之前，在铜籽晶层上沉积石墨烯牺牲层 从而为铜种子层沉积和镀铜之间的更长的队列时间（Q次）提供了工艺灵活性。 接下来，对石墨烯牺牲层进行等离子体处理，以在铜镀覆之前将障碍和缺陷引入到石墨烯牺牲层中以进行去除。 然后将整个结构浸入镀铜溶液中。 镀铜溶液溶解等离子体处理的石墨烯牺牲层，并在再曝光的铜籽晶层上形成含铜层。

公开(公告)号：US20160148931A1

公开(公告)日：2016-05-26

申请号：US14882618

申请日：2015-10-14

申请人： International Business Machines Corporation

发明人： Kangguo Cheng ,  Ali Khakifirooz ,  Richard S. Wise

IPC分类号： H01L27/092

CPC分类号： H01L29/7848 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02532 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/26566 ,  H01L21/266 ,  H01L21/31111 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656

摘要： A method of forming a complementary metal oxide semiconductor (CMOS) device structure includes forming a spacer layer material over a substrate and over gate structures defined in a first polarity type region and a second polarity type region; selectively etching the spacer layer material in the first polarity type region to form first gate sidewall spacers; forming first epitaxially grown source/drain (SD) regions in the first polarity type region; selectively forming a protection layer only on exposed surfaces of the first SD regions, so as not to increase a thickness of the spacer layer material in the second polarity type region; forming a masking layer over the first polarity type region, and etching the spacer layer material in the second polarity type region to form second gate sidewall spacers; and removing the masking layer and forming second epitaxially grown SD regions in the second polarity type region.

摘要翻译： 形成互补金属氧化物半导体（CMOS）器件结构的方法包括在衬底上形成间隔层材料，以及限定在第一极性类型区域和第二极性类型区域中的栅极结构; 选择性地蚀刻第一极性类型区域中的间隔层材料以形成第一栅极侧壁间隔物; 在第一极性类型区域中形成第一外延生长的源极/漏极（SD）区域; 仅在第一SD区域的暴露表面上选择性地形成保护层，以便不增加第二极性类型区域中间隔层材料的厚度; 在所述第一极性类型区域上形成掩模层，并且蚀刻所述第二极性类型区域中的间隔层材料以形成第二栅极侧壁间隔物; 以及去除所述掩模层并在所述第二极性类型区域中形成第二外延生长的SD区域。

公开(公告)号：US09324793B2

公开(公告)日：2016-04-26

申请号：US14871157

申请日：2015-09-30

申请人： International Business Machines Corporation ,  STMicroelectronics, Inc.

发明人： Lawrence A. Clevenger ,  Carl J. Radens ,  Richard S. Wise ,  Edem Wornyo ,  Yiheng Xu ,  John Zhang

IPC分类号： H01L21/461 ,  H01L23/58 ,  H01L29/06 ,  H01L29/66 ,  H01L51/05

CPC分类号： H01L29/0661 ,  H01L21/02071 ,  H01L21/0337 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32139 ,  H01L29/66621 ,  H01L29/66795 ,  H01L51/0525

摘要： An ashing chemistry employing a combination of Cl2 and N2 is provided, which removes residual material from sidewalls of a patterned metallic hard mask layer without residue such that the sidewalls of the patterned metallic hard mask layer are vertical. The vertical profiled of the sidewalls of the patterned metallic hard mask layer can be advantageously employed to reduce pattern factor dependency in the etch bias between the pattern transferred into an underlying layer and the pattern as formed on the metallic hard mask layer. Further, the ashing chemistry can be employed to enhance removal of stringers in vertical portions of a metallic material layer.

公开(公告)号：US09236447B2

公开(公告)日：2016-01-12

申请号：US14590238

申请日：2015-01-06

申请人： International Business Machines Corporation

发明人： Kangguo Cheng ,  Ali Khakifirooz ,  Richard S. Wise

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/6656 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7856 ,  H01L29/78606

摘要： A semiconductor device having asymmetric spacers and steps for forming the same are disclosed. The spacers have difference capacitances, with the spacer having a higher capacitance formed over a source region of the device and the spacer having a lower capacitance formed over a drain region of the device. Embodiments of the disclosed invention include spacers made from different materials, having different or substantially equal thicknesses.

摘要翻译： 公开了一种具有不对称间隔物的半导体器件及其形成步骤。 间隔物具有差异电容，间隔物在器件的源极区域上形成较高的电容，并且间隔物在器件的漏极区域上形成较低的电容。 所公开的发明的实施例包括由不同材料制成的间隔物，其具有不同的或基本相等的厚度。

公开(公告)号：US20140295674A1

公开(公告)日：2014-10-02

申请号：US13853088

申请日：2013-03-29

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kangguo Cheng ,  Ali Khakifirooz ,  Richard S. Wise

IPC分类号： H01J37/305 ,  H01L21/02 ,  C23C14/48 ,  C23C14/22 ,  H01J37/317

CPC分类号： C23C14/221 ,  C23C14/225 ,  H01J37/317 ,  H01J37/3171 ,  H01J37/3178 ,  H01J2237/0812 ,  H01J2237/20207 ,  H01L21/02274 ,  H01L21/31116 ,  H01L29/4983 ,  H01L29/66659

摘要： An angled gas cluster ion beam (“GCIB”) and methods for using the same are disclosed. Gas clusters are ionized to create a gas cluster beam directed towards a semiconductor wafer. The semiconductor wafer is positioned so that it intercepts the gas cluster beam at an angle that is non-perpendicular to the beam, so that the gas cluster ions in the beam react with structures on the semiconductor wafer asymmetrically, allowing for asymmetrical deposition on or etching of material thereon. According to one embodiment, GCIB is used to form asymmetric spacers having different materials, different thicknesses, or both.

摘要翻译： 公开了一种有角度的气体团簇离子束（“GCIB”）及其使用方法。 气体簇被电离以产生朝向半导体晶片的气体束束。 半导体晶片被定位成使得其以与垂直于光束非垂直的角度截取气体束束，使得光束中的气体团簇离子不对称地与半导体晶片上的结构反应，从而允许不对称沉积或蚀刻 的材料。 根据一个实施例，GCIB用于形成具有不同材料，不同厚度或两者的不对称间隔物。

公开(公告)号：US08771533B2

公开(公告)日：2014-07-08

申请号：US13780854

申请日：2013-02-28

申请人： International Business Machines Corporation

发明人： Mukta G. Farooq ,  Emily Kinser ,  Richard S. Wise ,  Hakeem B. S. Akinmade-Yusuff

IPC分类号： H01L21/02

CPC分类号： H01L21/02263 ,  H01L21/187 ,  H01L21/76898 ,  H01L25/074 ,  H01L25/50 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dielectric material layer is deposited on exposed surfaces of a bonded structure that includes a first substrate and a second substrate. The dielectric material layer is formed on an exposed planar surface of a second substrate and the entirety of peripheral sidewalls of the first and second substrates. The dielectric material layer can be formed by chemical vapor deposition, atomic layer deposition, or plasma induced deposition. Further, the dielectric material layer seals the entire periphery of the interface between the first and second substrates. If a planar portion of the dielectric material layer can be removed by planarization to facilitate thinning of the bonded structure, the remaining portion of the dielectric material layer can form a dielectric ring.

公开(公告)号：US20140103404A1

公开(公告)日：2014-04-17

申请号：US13653658

申请日：2012-10-17

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Ying Li ,  Ramachandra Divakaruni ,  Vijay Narayanan ,  Richard S. Wise

IPC分类号： H01L29/78 ,  H01L21/283

CPC分类号： H01L29/66553 ,  H01L21/28247 ,  H01L21/76897 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/66545

摘要： After formation of source and drain regions and a planarization dielectric layer, a disposable gate structure is removed to form a gate cavity. A gate dielectric and a lower gate electrode are formed within the gate cavity. The lower gate electrode is vertically recessed relative to the planarization dielectric layer to form a recessed region. An inner dielectric spacer is formed within the recessed region by depositing a conformal dielectric layer and removing horizontal portions thereof by an anisotropic etch. An upper gate electrode is formed by depositing another conductive material within a remaining portion of the recessed region. A contact level dielectric layer is formed and contact structures are formed to the source and drain regions. The inner dielectric spacer prevents an electrical short between the gate electrode and a contact structure that partially overlies the gate electrode by overlay variations during lithographic processes.

摘要翻译： 在形成源极和漏极区域和平坦化介电层之后，去除一次性栅极结构以形成栅极腔。 栅极电介质和下栅电极形成在栅极腔内。 下栅电极相对于平坦化电介质层垂直凹入以形成凹陷区域。 通过沉积保形介电层并通过各向异性蚀刻去除其水平部分，在凹陷区域内形成内部电介质间隔物。 通过在凹陷区域的剩余部分内沉积另一种导电材料来形成上部栅极电极。 形成接触电介质层，并且在源区和漏区形成接触结构。 内部电介质间隔物通过在光刻工艺期间的重叠变化来防止栅极电极和部分地覆盖栅电极的接触结构之间的电短路。