公开(公告)号：US07608920B2

公开(公告)日：2009-10-27

申请号：US11434964

申请日：2006-05-16

Applicant: James Douglas Wehrly, Jr.

Inventor： James Douglas Wehrly, Jr.

IPC: H01L23/02 ,  H01L21/48 ,  H01L23/04 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L25/105 ,  G06K19/07732 ,  H01L23/5387 ,  H01L23/5388 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H05K1/189 ,  H05K2201/10159 ,  H05K2201/10545 ,  H05K2201/10689 ,  H05K2201/2018 ,  H01L2924/00

Abstract: The present invention provides a system and method for employing leaded packaged memory devices in memory cards. Leaded packaged ICs are disposed on one or both sides of a flex circuitry structure to create an IC-populated structure. In a preferred embodiment, leads of constituent leaded IC packages are configured to allow the lower surface of the leaded IC packages to contact respective surfaces of the flex circuitry structure. Contacts for typical embodiments are supported by a rigid portion of the flex circuitry structure and the IC-populated structure is disposed in a casing to provide card structure for the module.

Abstract translation: 本发明提供一种在存储卡中采用引线封装的存储器件的系统和方法。 引线封装IC布置在柔性电路结构的一侧或两侧以产生IC填充结构。 在优选实施例中，构成引线IC封装的引线被配置为允许引线IC封装的下表面接触柔性电路结构的相应表面。 用于典型实施例的触头由柔性电路结构的刚性部分支撑，并且IC填充结构设置在壳体中以为模块提供卡结构。

公开(公告)号：US07586758B2

公开(公告)日：2009-09-08

申请号：US10958924

申请日：2004-10-05

Applicant: James W. Cady ,  James Wilder ,  David L. Roper ,  Russell Rapport ,  James Douglas Wehrly, Jr. ,  Jeffrey Alan Buchle

Inventor： James W. Cady ,  James Wilder ,  David L. Roper ,  Russell Rapport ,  James Douglas Wehrly, Jr. ,  Jeffrey Alan Buchle

IPC: H05K1/11 ,  H05K1/14

CPC classification number: H01L23/49816 ,  H01L23/3114 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2924/00012

Abstract: The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The present invention can be used to advantage with packages of a variety of sizes and configurations ranging from larger packaged base elements having many dozens of contacts to smaller packages such as, for example, die-sized packages such as DSBGA. In a preferred embodiment devised in accordance with the present invention, a base element CSP integrated circuit and a support element CSP integrated circuit are aggregated through a flex circuit having at least two conductive layers that are patterned to selectively connect the two CSP elements. A portion of the flex circuit connected to the support element is folded over the base element to dispose the support element above the base element while reducing the overall footprint. The flex circuit provides a thermal and electrical connection path between the module and an application environment such as a printed wiring board (PWB).

Abstract translation: 本发明将封装的集成电路堆叠成节省PWB或其他板表面积的模块。 本发明可以利用各种尺寸和配置的封装，其范围从具有许多触点的较大封装的基底元件到较小的封装，例如诸如DSBGA的裸片尺寸的封装。 在根据本发明设计的优选实施例中，基体元件CSP集成电路和支撑元件CSP集成电路通过具有图案化以选择性地连接两个CSP元件的至少两个导电层的柔性电路聚集。 连接到支撑元件的柔性电路的一部分折叠在基座元件上，以将支撑元件设置在基座元件上方，同时减小了总的占地面积。 柔性电路在模块和诸如印刷电路板（PWB）的应用环境之间提供热和电连接路径。

公开(公告)号：US07495334B2

公开(公告)日：2009-02-24

申请号：US11197267

申请日：2005-08-04

Applicant: Russell Rapport ,  James W. Cady ,  James Wilder ,  David L. Roper ,  James Douglas Wehrly, Jr. ,  Jeff Buchle ,  Julian Dowden

Inventor： Russell Rapport ,  James W. Cady ,  James Wilder ,  David L. Roper ,  James Douglas Wehrly, Jr. ,  Jeff Buchle ,  Julian Dowden

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/50 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01055 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2224/0401

Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. In a two-high CSP stack or module devised in accordance with a preferred embodiment of the present invention, two CSPs are stacked, with one CSP disposed above the other. The two CSPs are connected with flex circuitry. A form standard is disposed between the flex circuitry and a CSP in the stack. The form standard can take many configurations and may be used where flex circuits are used to connect CSPs to one another in stacked modules having two or more constituent CSPs. For example, in stacked modules that include four CSPs, three form standards are employed in preferred embodiments, although fewer may be used. The form standard provides a thermally conductive physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design.

Abstract translation: 本发明将芯片级封装集成电路（CSP）堆叠成保存PWB或其他板表面积的模块。 在根据本发明的优选实施例设计的两高CSP堆叠或模块中，堆叠两个CSP，其中一个CSP设置在另一个之上。 两个CSP与柔性电路连接。 在柔性电路和堆叠中的CSP之间设置一个形式标准。 形式标准可以采用许多配置，并且可以在柔性电路用于在具有两个或更多个组成CSP的堆叠模块中将CSP彼此连接的位置中使用。 例如，在包括四个CSP的堆叠模块中，在优选实施例中采用三个形式标准，尽管可以使用更少的标准。 形式标准提供导热物理形式，允许在广泛的CSP封装系列中找到许多变化的封装尺寸，同时采用标准连接柔性电路设计。

公开(公告)号：US07446410B2

公开(公告)日：2008-11-04

申请号：US11283355

申请日：2005-11-18

Applicant: James Douglas Wehrly, Jr. ,  James Wilder ,  Mark Wolfe ,  Paul Goodwin

Inventor： James Douglas Wehrly, Jr. ,  James Wilder ,  Mark Wolfe ,  Paul Goodwin

IPC: H01L23/34 ,  H01L21/00 ,  H05K7/20

CPC classification number: H05K1/189 ,  H05K1/0203 ,  H05K3/0061 ,  H05K2201/056 ,  H05K2201/09445 ,  H05K2201/10159 ,  H05K2201/1056 ,  H05K2201/10734 ,  H05K2203/1572

Abstract: Flexible circuitry is populated with integrated circuitry (ICs) disposed along one or both of major sides. Contacts are distributed along the flexible circuitry to provide connection between the module and an application environment. The populated flexible circuitry is disposed about an edge of a rigid substrate thus placing the integrated circuitry on one or both sides of the substrate with one or more layers of integrated circuitry on one or both sides of the substrate. The substrate form is preferably devised from thermally-conductive materials and one or more thermal spreaders are disposed in thermal contact with at least some of the constituent integrated circuitry of the module. Optionally, as an additional thermal management feature, the module may include a high thermal conductivity thermal sink or area that is disposed proximal to higher thermal energy IC devices. In preferred embodiments, extensions from the substrate body or substrate core encourage reduced thermal variations amongst the ICs of the module while providing an enlarged surface for shedding thermal energy from the module.

Abstract translation: 灵活的电路装有沿主要侧面或两侧设置的集成电路（IC）。 触点沿柔性电路分布，以提供模块与应用环境之间的连接。 填充的柔性电路围绕刚性衬底的边缘设置，从而将集成电路放置在衬底的一侧或两侧上，在衬底的一侧或两侧上具有一层或多层集成电路。 衬底形式优选地由导热材料设计，并且一个或多个热扩散器设置成与模块的组成集成电路中的至少一些热接触。 可选地，作为附加的热管理特征，模块可以包括设置在较高热能IC器件附近的高导热性散热器或区域。 在优选实施例中，来自衬底主体或衬底芯的延伸部促进模块的IC之间的热变化减小，同时提供用于从模块中排出热能的扩大表面。

公开(公告)号：US07335975B2

公开(公告)日：2008-02-26

申请号：US10958934

申请日：2004-10-05

Applicant: James W. Cady ,  James Wilder ,  David L. Roper ,  Russell Rapport ,  James Douglas Wehrly, Jr. ,  Jeffrey Alan Buchle

Inventor： James W. Cady ,  James Wilder ,  David L. Roper ,  Russell Rapport ,  James Douglas Wehrly, Jr. ,  Jeffrey Alan Buchle

IPC: H01L23/48

CPC classification number: H01L23/49816 ,  H01L23/3114 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2924/00012

Abstract: The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The invention provides techniques and structures for aggregating chip scale-packaged integrated circuits (CSPs) or leaded packages with other CSPs or with monolithic or stacked leaded packages into modules that conserve PWB or other board surface area. The present invention can be used to advantage with packages of a variety of sizes and configurations ranging from larger packaged base elements having many dozens of contacts to smaller packages such as, for example, die-sized packages such as DSBGA. In a preferred embodiment devised in accordance with the present invention, a base element CSP and a support element CSP are aggregated through a flex circuit having at least two conductive layers that are patterned to selectively connect the two CSP elements. The flex circuit connects the ICs and provides a thermal and electrical connection path between the module and an application environment such as a printed wiring board (PWB).

Abstract translation: 本发明将封装的集成电路堆叠成节省PWB或其他板表面积的模块。 本发明提供了用于将芯片级封装集成电路（CSP）或具有其他CSP的引线封装或者将单片或堆叠引线封装集成到节省PWB或其他板表面积的模块中的技术和结构。 本发明可以利用各种尺寸和配置的封装，其范围从具有许多触点的较大封装的基底元件到较小的封装，例如诸如DSBGA的裸片尺寸的封装。 在根据本发明设计的优选实施例中，基体元件CSP和支撑元件CSP通过具有图案化以选择性地连接两个CSP元件的至少两个导电层的柔性电路聚集。 柔性电路连接IC，并在模块和诸如印刷电路板（PWB）的应用环境之间提供热和电连接路径。

公开(公告)号：US06956284B2

公开(公告)日：2005-10-18

申请号：US10814532

申请日：2004-03-31

Applicant: James W. Cady ,  James Wilder ,  David L. Roper ,  James Douglas Wehrly, Jr.

Inventor： James W. Cady ,  James Wilder ,  David L. Roper ,  James Douglas Wehrly, Jr.

IPC: H01L23/02 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36

CPC classification number: H01L23/3114 ,  H01L23/4985 ,  H01L23/5386 ,  H01L23/5387 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01055 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2224/0401

Abstract: The present invention stacks integrated circuits (ICs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In an alternative embodiment, the form standard may include a heat spreader portion with mounting feet. In a preferred embodiment of the memory addressing system, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access.

Abstract translation: 本发明将集成电路（IC）堆叠成节省PWB或其他板表面积的模块。 在另一方面，本发明提供了一种较低电容存储器扩展寻址系统和方法，并且优选地具有本文提供的CSP堆叠模块。 在根据本发明的优选实施例中，形式标准提供了一种物理形式，其允许在广泛的CSP封装系列中发现的许多变化的封装尺寸在使用标准连接柔性电路设计时被有利地使用。 在优选实施例中，将设计形式标准，以便传热材料例如铜，以改善热性能。 在替代实施例中，形式标准可以包括具有安装支脚的散热器部分。 在存储器寻址系统的优选实施例中，高速交换系统选择与堆叠模块的每个级别相关联的数据线，以减少对存储器访问中的数据信号的负载影响。

公开(公告)号：US06576992B1

公开(公告)日：2003-06-10

申请号：US10005581

申请日：2001-10-26

Applicant: James W. Cady ,  James Wilder ,  David L. Roper ,  James Douglas Wehrly, Jr. ,  Julian Dowden ,  Jeff Buchle

Inventor： James W. Cady ,  James Wilder ,  David L. Roper ,  James Douglas Wehrly, Jr. ,  Julian Dowden ,  Jeff Buchle

IPC: H05K706

CPC classification number: H05K1/141 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/01087 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734

Abstract: The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve board surface area. In a two-high CSP stack or module devised in accordance with a preferred embodiment of the present invention, a pair of CSPs is stacked, with one CSP above the other. The two CSPs are connected with a pair of flexible circuit structures. Each of the pair of flexible circuit structures is partially wrapped about a respective opposite lateral edge of the lower CSP of the module. The flex circuit pair connects the upper and lower CSPs and provides a thermal and electrical connection path between the module and an application environment such as a printed wiring board (PWB). The present invention may be employed to advantage in numerous configurations and combinations of CSPs in modules provided for high-density memories or high capacity computing.

Abstract translation: 本发明将芯片级封装集成电路（CSP）堆叠成节省板表面积的模块。 在根据本发明的优选实施例设计的两高CSP堆栈或模块中，堆叠一对CSP，其中一个CSP在另一CSP之上。 两个CSP与一对柔性电路结构连接。 一对柔性电路结构中的每一个部分地围绕模块的下CSP的相应的相对侧边缘缠绕。 柔性电路对连接上部和下部CSP，并且在模块和诸如印刷线路板（PWB）的应用环境之间提供热和电连接路径。 本发明可以有利于提供用于高密度存储器或高容量计算的模块中的CSP的多种配置和组合。

公开(公告)号：US07656678B2

公开(公告)日：2010-02-02

申请号：US11263627

申请日：2005-10-31

Applicant: Julian Partridge ,  James Douglas Wehrly, Jr. ,  David L. Roper ,  Joseph Villani

Inventor： Julian Partridge ,  James Douglas Wehrly, Jr. ,  David L. Roper ,  Joseph Villani

IPC: H05K7/10 ,  H05K7/12

CPC classification number: H01L23/49833 ,  H01L23/5385 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06579 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K3/305 ,  H05K2201/056 ,  H05K2201/10734 ,  Y02P70/613 ,  H01L2224/0401

Abstract: The present invention stacks integrated circuit packages into circuit modules. In a preferred embodiment, solder paste and primary adhesive respectively are applied to selected locations on the flex circuitry. Supplemental adhesive is applied to additional locations on the flex circuitry, CSP, or other component. The flex circuitry and the CSP are brought into proximity with each other. During solder reflow operation, a force is applied and the CSP collapses toward the flex circuitry, displacing the primary adhesive and the supplemental adhesive. The supplemental adhesive establishes a bond providing additional support to the flex circuitry. In another embodiment, CSPs or other integrated circuit packages are bonded to each other or to other components with a combination of adhesives. A rapid bond adhesive maintains alignment of the bonded packages and/or components during assembly, and a structural bond adhesive provides additional strength and/or structural integrity to the bond.

Abstract translation: 本发明将集成电路封装堆叠成电路模块。 在优选实施例中，焊膏和主粘合剂分别施加到柔性电路上的选定位置。 补充粘合剂应用于柔性电路，CSP或其他部件上的附加位置。 柔性电路和CSP彼此接近。 在回流焊接操作期间，施加力并且CSP朝向柔性电路折叠，使主粘合剂和补充粘合剂移位。 补充粘合剂建立了粘合，为柔性电路提供额外的支撑。 在另一个实施例中，CSP或其他集成电路封装通过粘合剂的组合彼此结合或连接到其它部件。 快速粘合粘合剂在组装期间保持粘合的包装和/或部件的对准，并且结构粘合粘合剂为粘合剂提供附加的强度和/或结构完整性。

公开(公告)号：US07616452B2

公开(公告)日：2009-11-10

申请号：US11331969

申请日：2006-01-13

Applicant: James Douglas Wehrly, Jr. ,  Paul Goodwin ,  Russell Rapport

Inventor： James Douglas Wehrly, Jr. ,  Paul Goodwin ,  Russell Rapport

IPC: H05K1/11

CPC classification number: H05K1/189 ,  H05K1/0203 ,  H05K1/11 ,  H05K1/181 ,  H05K3/0061 ,  H05K2201/056 ,  H05K2201/09445 ,  H05K2201/10159 ,  H05K2201/1056 ,  H05K2201/10734 ,  H05K2203/1572

Abstract: Provided circuit modules employ flexible circuitry populated with integrated circuitry (ICs). The flex circuitry is disposed about a rigid substrate. Contacts distributed along the flexible circuitry provide connection between the module and an application environment. A strain relief portion of the flex circuitry has preferably fewer layers than the portion of the flex circuitry along which the integrated circuitry is disposed and may further may exhibit more flexibility than the portion of the flex circuit populated with integrated circuitry. The substrate form is preferably devised from thermally conductive materials.

Abstract translation: 所提供的电路模块采用装有集成电路（IC）的灵活电路。 柔性电路围绕刚性衬底设置。 沿柔性电路分布的触点提供模块与应用环境之间的连接。 柔性电路的应变消除部分优选地比柔性电路的布置集成电路的部分更少的层，并且还可以表现出比装有集成电路的柔性电路的部分更多的灵活性。 底物形式优选地由导热材料设计。

公开(公告)号：US07606048B2

公开(公告)日：2009-10-20

申请号：US10958584

申请日：2004-10-05

Applicant: James W. Cady ,  James Wilder ,  David L. Roper ,  Russell Rapport ,  James Douglas Wehrly, Jr. ,  Jeffrey Alan Buchle

Inventor： James W. Cady ,  James Wilder ,  David L. Roper ,  Russell Rapport ,  James Douglas Wehrly, Jr. ,  Jeffrey Alan Buchle

IPC: H05K7/10 ,  H05K7/12

CPC classification number: H01L23/49816 ,  H01L23/3114 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2924/00012

Abstract: The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The present invention can be used to advantage with packages of a variety of sizes and configurations ranging from larger packaged base elements having many dozens of contacts to smaller packages such as, for example, die-sized packages such as DSBGA. In a preferred embodiment devised in accordance with the present invention, a base element CSP integrated circuit and a support element CSP integrated circuit are aggregated through a flex circuit having at least two conductive layers that are patterned to selectively connect the two CSP elements. A portion of the flex circuit connected to the support element is folded over the base element to dispose the support element above the base element while reducing the overall footprint. The flex circuit provides a thermal and electrical connection path between the module and an application environment such as a printed wiring board (PWB).