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公开(公告)号:US20190244979A1
公开(公告)日:2019-08-08
申请号:US15929125
申请日:2019-04-18
Applicant: Japan Display Inc.
Inventor: Isao SUZUMURA , Yohei YAMAGUCHI , Hajime WATAKABE , Akihiro HANADA , Hirokazu WATANABE , Marina SHIOKAWA
IPC: H01L27/12 , H01L29/49 , H01L21/02 , H01L29/786 , H01L29/66 , H01L21/4763 , H01L21/465
CPC classification number: H01L27/1225 , G02F1/133305 , G02F1/13452 , G02F1/136227 , G02F1/136286 , G02F1/1368 , G02F2001/136295 , G02F2202/10 , H01L21/02164 , H01L21/0217 , H01L21/02178 , H01L21/02565 , H01L21/465 , H01L21/47635 , H01L27/1218 , H01L27/124 , H01L27/1248 , H01L27/1266 , H01L27/127 , H01L27/3248 , H01L27/3262 , H01L27/3276 , H01L29/42384 , H01L29/4908 , H01L29/4983 , H01L29/66969 , H01L29/78648 , H01L29/7869
Abstract: A display device to improve reliability of the TFT of the oxide semiconductor, including: a substrate including a display area where plural pixels are formed, the pixel includes a first TFT of a first oxide semiconductor; a first gate insulating film is formed on the first oxide semiconductor, a gate electrode is formed on the first gate insulating film, an interlayer insulating film is formed over the gate electrode; the gate insulating film includes a first silicon oxide film, the gate electrode includes a first gate layer made of a second oxide semiconductor and a second gate layer made of metal or alloy; the interlayer insulating film has a first interlayer insulating film including a second silicon oxide film, and a second interlayer insulating film including a first aluminum oxide film on the first interlayer insulating film.
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公开(公告)号:US20190096915A1
公开(公告)日:2019-03-28
申请号:US16200157
申请日:2018-11-26
Applicant: Japan Display Inc.
Inventor: Akihiro HANADA , Masayoshi FUCHI
IPC: H01L27/12 , H01L23/532 , H01L29/786 , H01L23/522 , H01L21/768 , H01L21/02
CPC classification number: H01L27/124 , H01L21/02063 , H01L21/76802 , H01L21/76843 , H01L21/76877 , H01L23/5226 , H01L23/53223 , H01L23/53266 , H01L27/1218 , H01L27/1222 , H01L27/1225 , H01L27/1262 , H01L29/78603 , H01L29/78675 , H01L29/7869
Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer located above the insulating substrate, a second semiconductor layer located above the insulating substrate, an insulating layer which covers the first semiconductor layer and the second semiconductor layer, and includes a first contact hole reaching the first semiconductor layer and a second contact hole reaching the second semiconductor layer, a barrier layer which covers one of the first semiconductor layer inside the first contact hole and the second semiconductor layer inside the second contact hole, and a first conductive layer which is in contact with the barrier layer.
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公开(公告)号:US20190041932A1
公开(公告)日:2019-02-07
申请号:US16131477
申请日:2018-09-14
Applicant: Japan Display Inc.
Inventor: Akihiro HANADA , Hajime Watakabe , Kazufumi Watabe
Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer formed of silicon and positioned above the insulating substrate, a second semiconductor layer formed of a metal oxide and positioned above the first semiconductor layer, a first insulating film formed of a silicon nitride and positioned between the first semiconductor layer and the second semiconductor layer, and a block layer positioned between the first semiconductor film and the second semiconductor layer, the block layer hydrogen diffusion of which is lower than that of the first insulating film.
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公开(公告)号:US20250113616A1
公开(公告)日:2025-04-03
申请号:US18884253
申请日:2024-09-13
Applicant: Japan Display Inc.
Inventor: Akihiro HANADA , Takuo KAITOH , Motochika YUKAWA
IPC: H01L27/12 , G02F1/1368
Abstract: A display device includes an oxide semiconductor layer including a polycrystalline structure, a gate insulating layer provided on the oxide semiconductor layer, a gate electrode opposite to the oxide semiconductor layer on the gate insulating layer, a first silicon nitride layer provided in contact with the gate electrode, a source wiring provided in contact with the first silicon nitride layer and electrically connected to the oxide semiconductor layer, a second silicon nitride layer provided in contact with the source wiring and the first silicon nitride layer, a first transparent conductive layer provided in contact with the second silicon nitride layer and electrically connected to the oxide semiconductor layer, and a third silicon nitride layer provided in contact with the first transparent conductive layer and the second silicon nitride layer, wherein a channel length of the gate electrode is 2.0 μm or less.
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公开(公告)号:US20250113543A1
公开(公告)日:2025-04-03
申请号:US18895479
申请日:2024-09-25
Applicant: Japan Display Inc.
Inventor: Hajime WATAKABE , Masashi TSUBUKU , Kentaro MIURA , Akihiro HANADA , Masahiro WATABE
IPC: H01L29/786 , H01L29/423
Abstract: A semiconductor device according to an embodiment of the present invention includes an oxide semiconductor layer having a polycrystalline structure and including an impurity region containing an impurity element, a gate electrode over the oxide semiconductor layer, an insulating layer between the oxide semiconductor layer and the gate electrode, a first contact hole penetrating the insulating layer and exposing the impurity region, a second contact hole penetrating at least the insulating layer and having a greater depth than the first contact hole, and a connection wiring electrically connecting the impurity region to a layer which is exposed in the second contact hole through the first contact hole and the second contact hole. The connection wiring includes a first conductive layer and a second conductive layer on the first conductive layer. A portion of the first conductive layer that is exposed from the second conductive layer contains the impurity element.
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公开(公告)号:US20240402553A1
公开(公告)日:2024-12-05
申请号:US18673809
申请日:2024-05-24
Applicant: Japan Display Inc.
Inventor: Akihiro HANADA , Takuo KAITOH , Ryo ONODERA , Motochika YUKAWA
IPC: G02F1/1362 , G02F1/1368
Abstract: A display device includes a first conductive layer arranged on a first substrate and extending in a first direction, a first insulating film arranged on the first conductive layer, a second conductive layer arranged on the first insulating film and extending in a second direction intersecting the first direction, a second insulating film arranged on the second conductive layer and extending in the first direction and the second direction, a transparent conductive layer arranged on the second insulating film and extending in the first direction and the second direction, a third insulating film arranged on the first conductive layer, and a second substrate opposing the first substrate.
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公开(公告)号:US20240369891A1
公开(公告)日:2024-11-07
申请号:US18777958
申请日:2024-07-19
Applicant: Japan Display Inc.
Inventor: Akihiro HANADA , Toshihide JINNAI , Isao SUZUMURA , Hajime WATAKABE , Ryo ONODERA
IPC: G02F1/1368 , G02F1/1362 , H01L29/786 , H10K50/86 , H10K59/131
Abstract: A display device including: a substrate; a first thin film transistor of polysilicon semiconductor, a second thin film transistor of oxide semiconductor; a first light shading film opposing to the polysilicon semiconductor, and a second light shading film opposing to the oxide semiconductor; a first insulating film, a second insulating film which is constituted from plural insulating films, and a third insulating film superposed in this order; a first through hole penetrating the second insulating film and not penetrating the first insulating film and the third insulating film; a second through hole penetrating the first insulating film and the third insulating film; the first light shading film connects with a first conductive component, a part of the first conductive component exists on the third insulating film, through the second through hole.
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公开(公告)号:US20240088166A1
公开(公告)日:2024-03-14
申请号:US18509459
申请日:2023-11-15
Applicant: Japan Display Inc.
Inventor: Akihiro HANADA , Masayoshi FUCHI
IPC: H01L27/12 , H01L21/02 , H01L21/768 , H01L23/522 , H01L23/532 , H01L29/786
CPC classification number: H01L27/124 , H01L21/02063 , H01L21/76802 , H01L21/76843 , H01L21/76877 , H01L23/5226 , H01L23/53223 , H01L23/53266 , H01L27/1218 , H01L27/1222 , H01L27/1225 , H01L27/1262 , H01L29/78603 , H01L29/78675 , H01L29/7869
Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer located above the insulating substrate, a second semiconductor layer located above the insulating substrate, an insulating layer which covers the first semiconductor layer and the second semiconductor layer, and includes a first contact hole reaching the first semiconductor layer and a second contact hole reaching the second semiconductor layer, a barrier layer which covers one of the first semiconductor layer inside the first contact hole and the second semiconductor layer inside the second contact hole, and a first conductive layer which is in contact with the barrier layer.
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公开(公告)号:US20230350257A1
公开(公告)日:2023-11-02
申请号:US18349217
申请日:2023-07-10
Applicant: Japan Display Inc.
Inventor: Tatsunori MURAMOTO , Kentaro KAWAI , Yoshihide OHUE , Akihiro HANADA
IPC: G02F1/1368 , H01L27/12 , G02F1/1334 , G02F1/1362
CPC classification number: G02F1/1368 , H01L27/1248 , G02F1/1334 , G02F1/136286
Abstract: According to one embodiment, a display device includes a first substrate including a first transparent substrate, a switching element including an oxide semiconductor, an organic insulating film covering the switching element, a transparent electrode including a first aperture penetrating to an upper surface of the organic insulating film, an inorganic insulating film including a second aperture penetrating to the upper surface in the first aperture, and a pixel electrode electrically connected to the switching element, and a second substrate including a second transparent substrate and opposed to the first substrate.
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公开(公告)号:US20230253506A1
公开(公告)日:2023-08-10
申请号:US18163286
申请日:2023-02-02
Applicant: Japan Display Inc.
Inventor: Ryo ONODERA , Akihiro HANADA , Takuo KAITOH , Tomoyuki ITO
IPC: H01L29/786 , G02F1/1362 , G02F1/1368
CPC classification number: H01L29/7869 , G02F1/136286 , G02F1/1368
Abstract: According to one embodiment, a semiconductor device includes a first gate electrode formed to be integrated with a scanning line, an oxide semiconductor layer, a first signal line and a second signal line in contact with the oxide semiconductor layer, and a second gate electrode disposed opposing the first gate electrode with the oxide semiconductor layer interposed therebetween, and connected to the first gate electrode, wherein the second gate electrode does not overlap the first signal line, but overlaps the second signal line.
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