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    Image sensor including spatially different active and dark pixel interconnect patterns
    11.
    发明授权
    Image sensor including spatially different active and dark pixel interconnect patterns 有权
    图像传感器包括空间不同的有源和暗像素互连图案

    公开(公告)号：US07825416B2

    公开(公告)日：2010-11-02

    申请号：US12423055

    申请日：2009-04-14

    申请人： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel

    发明人： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel

    IPC分类号： H01L29/786

    CPC分类号： H01L27/14636 ,  H01L27/14603 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14645 ,  H01L27/14687

    摘要： An interconnect layout, an image sensor including the interconnect layout and a method for fabricating the image sensor each use a first electrically active physical interconnect layout pattern within an active pixel region and a second electrically active physical interconnect layout pattern spatially different than the first electrically active physical interconnect layout pattern within a dark pixel region. The second electrically active physical interconnect layout pattern includes at least one electrically active interconnect layer interposed between a light shield layer and a photosensor region aligned therebeneath, thus generally providing a higher wiring density. The higher wiring density within the second layout pattern provides that that the image sensor may be fabricated with enhanced manufacturing efficiency and a reduction of metallization levels.

    摘要翻译： 互连布局，包括互连布局的图像传感器和用于制造图像传感器的方法各自使用有源像素区域内的第一电活性物理互连布局图案和在空间上不同于第一电活动的第二电活动物理互连布局图案 物理互连布局图案在暗像素区域内。 第二电活动物理互连布局图案包括插入在遮光层和在其下对准的光电传感器区域之间的至少一个电活动互连层，因此通常提供更高的布线密度。 在第二布局图案中更高的布线密度提供了图像传感器可以制造成具有增强的制造效率和金属化水平的降低。

    IMAGE SENSOR INCLUDING SPATIALLY DIFFERENT ACTIVE AND DARK PIXEL INTERCONNECT PATTERNS
    13.
    发明申请
    IMAGE SENSOR INCLUDING SPATIALLY DIFFERENT ACTIVE AND DARK PIXEL INTERCONNECT PATTERNS 有权
    图像传感器包括空间不同的主动和深色像素互连图案

    公开(公告)号：US20090224349A1

    公开(公告)日：2009-09-10

    申请号：US12423055

    申请日：2009-04-14

    申请人： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel

    发明人： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel

    IPC分类号： H01L31/0232 ,  H01L31/0224

    CPC分类号： H01L27/14636 ,  H01L27/14603 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14645 ,  H01L27/14687

    摘要： An interconnect layout, an image sensor including the interconnect layout and a method for fabricating the image sensor each use a first electrically active physical interconnect layout pattern within an active pixel region and a second electrically active physical interconnect layout pattern spatially different than the first electrically active physical interconnect layout pattern within a dark pixel region. The second electrically active physical interconnect layout pattern includes at least one electrically active interconnect layer interposed between a light shield layer and a photosensor region aligned therebeneath, thus generally providing a higher wiring density. The higher wiring density within the second layout pattern provides that that the image sensor may be fabricated with enhanced manufacturing efficiency and a reduction of metallization levels.

    摘要翻译： 互连布局，包括互连布局的图像传感器和用于制造图像传感器的方法各自使用有源像素区域内的第一电活性物理互连布局图案和在空间上不同于第一电活动的第二电活动物理互连布局图案 物理互连布局图案在暗像素区域内。 第二电活动物理互连布局图案包括插入在遮光层和在其下对准的光电传感器区域之间的至少一个电活动互连层，因此通常提供更高的布线密度。 在第二布局图案中更高的布线密度提供了图像传感器可以制造成具有增强的制造效率和金属化水平的降低。

    Image sensor including spatially different active and dark pixel interconnect patterns
    14.
    发明授权
    Image sensor including spatially different active and dark pixel interconnect patterns 有权
    图像传感器包括空间不同的有源和暗像素互连图案

    公开(公告)号：US07537951B2

    公开(公告)日：2009-05-26

    申请号：US11560019

    申请日：2006-11-15

    申请人： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel

    发明人： Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel

    IPC分类号： H01L21/00

    CPC分类号： H01L27/14636 ,  H01L27/14603 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14645 ,  H01L27/14687

    摘要： An interconnect layout, an image sensor including the interconnect layout and a method for fabricating the image sensor each use a first electrically active physical interconnect layout pattern within an active pixel region and a second electrically active physical interconnect layout pattern spatially different than the first electrically active physical interconnect layout pattern within a dark pixel region. The second electrically active physical interconnect layout pattern includes at least one electrically active interconnect layer interposed between a light shield layer and a photosensor region aligned therebeneath, thus generally providing a higher wiring density. The higher wiring density within the second layout pattern provides that that the image sensor may be fabricated with enhanced manufacturing efficiency and a reduction of metallization levels.

    摘要翻译： 互连布局，包括互连布局的图像传感器和用于制造图像传感器的方法各自使用有源像素区域内的第一电活性物理互连布局图案和在空间上不同于第一电活动的第二电活动物理互连布局图案 物理互连布局图案在暗像素区域内。 第二电活动物理互连布局图案包括插入在遮光层和在其下对准的光电传感器区域之间的至少一个电活动互连层，因此通常提供更高的布线密度。 在第二布局图案中更高的布线密度提供了图像传感器可以制造成具有增强的制造效率和金属化水平的降低。

    Pixel sensor cells and methods of manufacturing
    16.
    发明授权
    Pixel sensor cells and methods of manufacturing 有权
    像素传感器单元和制造方法

    公开(公告)号：US08592244B2

    公开(公告)日：2013-11-26

    申请号：US13189961

    申请日：2011-07-25

    申请人： Jeffrey P. Gambino ,  Robert K. Leidy ,  Mark D. Levy

    发明人： Jeffrey P. Gambino ,  Robert K. Leidy ,  Mark D. Levy

    IPC分类号： H01L21/00

    CPC分类号： H01L27/14623 ,  H01L27/14636 ,  H01L27/14687

    摘要： Pixel sensor cells with an opaque mask layer and methods of manufacturing are provided. The method includes forming a transparent layer over at least one active pixel and at least one dark pixel of a pixel sensor cell. The method further includes forming an opaque region in the transparent layer over the at least one dark pixel.

    摘要翻译： 提供了具有不透明掩模层的像素传感器单元和制造方法。 该方法包括在像素传感器单元的至少一个有源像素和至少一个暗像素的上方形成透明层。 该方法还包括在至少一个暗像素上的透明层中形成不透明区域。

    THICK BOND PAD FOR CHIP WITH CAVITY PACKAGE
    17.
    发明申请
    THICK BOND PAD FOR CHIP WITH CAVITY PACKAGE 有权
    厚重的包装用于芯片

    公开(公告)号：US20110068424A1

    公开(公告)日：2011-03-24

    申请号：US12564996

    申请日：2009-09-23

    申请人： Jeffrey P. Gambino ,  Robert K. Leidy ,  Richard J. Rassel

    发明人： Jeffrey P. Gambino ,  Robert K. Leidy ,  Richard J. Rassel

    IPC分类号： H01L31/0232

    CPC分类号： H01L27/14687 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5384 ,  H01L31/0203 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed herein an image sensor chip, including a substrate having at least one via extending through at least one inter layer dielectric (ILD); a first conductive layer over the ILD, wherein the first conductive layer has a first thickness; a second conductive layer over the first conductive layer, wherein the second conductive layer has a second thickness of less than the first thickness; a polymer layer over the second conductive layer, the polymer layer including a cavity; a plurality of cavity components in the cavity; and an optically transparent layer contacting the polymer layer and covering the cavity.

    摘要翻译： 本文公开了一种图像传感器芯片，包括具有延伸穿过至少一个层间电介质（ILD）的至少一个通孔的基板; ILD上的第一导电层，其中所述第一导电层具有第一厚度; 在所述第一导电层上的第二导电层，其中所述第二导电层具有小于所述第一厚度的第二厚度; 在所述第二导电层上的聚合物层，所述聚合物层包括空腔; 空腔中的多个空腔部件; 以及与聚合物层接触并覆盖空腔的光学透明层。

    CMOS imager with Cu wiring and method of eliminating high reflectivity interfaces therefrom
    18.
    发明授权
    CMOS imager with Cu wiring and method of eliminating high reflectivity interfaces therefrom 失效
    具有Cu布线的CMOS成像器和从其中消除高反射率界面的方法

    公开(公告)号：US07772028B2

    公开(公告)日：2010-08-10

    申请号：US11959841

    申请日：2007-12-19

    申请人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel ,  Anthony K. Stamper

    发明人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel ,  Anthony K. Stamper

    IPC分类号： H01L21/66

    CPC分类号： H01L27/14636 ,  H01L21/76819 ,  H01L21/76834 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14645 ,  H01L27/14683

    摘要： A CMOS image sensor and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity. The CMOS image sensor includes structures having a minimum thickness of barrier layer metal that traverses the optical path of each pixel in the sensor array or, that have portions of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer may be formed atop the Cu metallization by a self-aligned deposition.

    摘要翻译： CMOS图像传感器和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合较薄的层间电介质堆叠以产生呈现增加的光灵敏度的像素阵列。 CMOS图像传感器包括具有穿过传感器阵列中的每个像素的光路的阻挡层金属的最小厚度的结构，或者具有从每个像素的光路中选择性地去除的阻挡层金属的部分，从而使反射率最小化的结构。 也就是说，通过实现各种块或单掩模方法，在阵列中的每个像素的光路的位置处完全去除了阻挡层金属的部分。 在另一个实施例中，阻挡金属层可以通过自对准沉积形成在Cu金属化之上。

    Damascene copper wiring optical image sensor
    19.
    发明授权
    Damascene copper wiring optical image sensor 有权
    大马士革铜线接线光学图像传感器

    公开(公告)号：US07655495B2

    公开(公告)日：2010-02-02

    申请号：US11623977

    申请日：2007-01-17

    申请人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Anthony K. Stamper

    发明人： James W. Adkisson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Anthony K. Stamper

    IPC分类号： H01L21/00

    CPC分类号： H01L27/14685 ,  H01L21/76819 ,  H01L21/76834 ,  H01L21/76838 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14687

    摘要： A CMOS image sensor array and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack with improved thickness uniformity to result in a pixel array exhibiting increased light sensitivity. In the sensor array, each Cu metallization level includes a Cu metal wire structure formed at locations between each array pixel and, a barrier material layer is formed on top each Cu metal wire structure that traverses the pixel optical path. By implementing a single mask or self-aligned mask methodology, a single etch is conducted to completely remove the interlevel dielectric and barrier layers that traverse the optical path. The etched opening is then refilled with dielectric material. Prior to depositing the refill dielectric, a layer of either reflective or absorptive material is formed along the sidewalls of the etched opening to improve sensitivity of the pixels by either reflecting light to the underlying photodiode or by eliminating light reflections.

    摘要翻译： CMOS图像传感器阵列和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合更薄的层间电介质叠层，具有改进的厚度均匀性，以产生呈现增加的光敏度的像素阵列。 在传感器阵列中，每个Cu金属化层包括在每个阵列像素之间的位置处形成的Cu金属线结构，并且阻挡材料层形成在穿过像素光路的每个Cu金属线结构上。 通过实现单掩模或自对准掩模方法，进行单次蚀刻以完全去除穿过光路的层间电介质层和阻挡层。 然后将蚀刻的开口用电介质材料重新填充。 在沉积再充填电介质之前，沿蚀刻开口的侧壁形成反射或吸收材料层，以通过将光反射到下面的光电二极管或通过消除光反射来提高像素的灵敏度。