公开(公告)号：US20050263753A1

公开(公告)日：2005-12-01

申请号：US11179282

申请日：2005-07-12

申请人： Mario Pelella ,  Simon Chan

发明人： Mario Pelella ,  Simon Chan

IPC分类号： C30B25/18 ,  H01L21/20 ,  H01L21/304 ,  H01L21/762 ,  H01L29/06

CPC分类号： H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/3043 ,  H01L29/7842

摘要： An integrated circuit (IC) utilizes a strained layer. The substrate can utilize trenches in a base layer to induce stress in a layer. The trenches define pillars on a back side of a bulk substrate or base layer of a semiconductor-on-insulator (SOI) wafer.

摘要翻译： 集成电路（IC）利用应变层。 衬底可以利用基层中的沟槽以在层中诱导应力。 沟槽在绝缘体上半导体（SOI）晶片的体基板或基底层的背侧上限定支柱。

公开(公告)号：US20050158963A1

公开(公告)日：2005-07-21

申请号：US10759207

申请日：2004-01-20

申请人： Darin Chan ,  Simon Chan ,  Angela Hui

发明人： Darin Chan ,  Simon Chan ,  Angela Hui

IPC分类号： H01L21/762 ,  H01L21/76 ,  H01L21/336

CPC分类号： H01L21/76224

摘要： Planarized STI with minimized topography is formed by selectively etching back the dielectric trench fill with respect to the polish stop film prior to removing the polish stop film. Embodiments include etching back a silicon oxide trench filled to a depth of about 200 Å to about 1,500 Å, and then stripping a silicon nitride polish stop layer leaving a substantially planarized surface, thereby improving the accuracy of subsequent gate electrode patterning and reducing stringers.

摘要翻译： 通过在去除抛光停止膜之前相对于抛光止挡膜选择性地蚀刻回介质沟槽填充物而形成具有最小化形貌的平坦化STI。 实施例包括将填充至大约至大约深度的氧化硅沟槽刻蚀，然后剥离留下基本平坦化表面的氮化硅抛光停止层，从而提高随后的栅电极图案化和减少桁条的精度。

公开(公告)号：US06417571B1

公开(公告)日：2002-07-09

申请号：US09516343

申请日：2000-03-01

申请人： Takeshi Nogami ,  Simon Chan

发明人： Takeshi Nogami ,  Simon Chan

IPC分类号： H01L2348

CPC分类号： H01L21/76877 ,  H01L21/76841

摘要： A system and method for providing copper interconnect in a trench formed in a dielectric is disclosed. In one aspect, the method and system include providing a copper layer; removing a portion of the copper layer outside of the trench; annealing the copper layer; and providing a layer disposed above the copper layer. In another aspect, the method and system include providing a copper interconnect formed in a trench on a dielectric. The copper interconnect includes a copper layer disposed in the trench and a layer disposed above the copper layer. The copper layer has a bamboo structure at least one grain. The at least one grain has substantially one orientation.

摘要翻译： 公开了一种用于在形成在电介质中的沟槽中提供铜互连的系统和方法。 一方面，所述方法和系统包括提供铜层; 去除所述沟槽外部的所述铜层的一部分; 退火铜层; 并提供设置在铜层之上的层。 在另一方面，该方法和系统包括提供形成在电介质上的沟槽中的铜互连。 铜互连包括设置在沟槽中的铜层和设置在铜层上方的层。 铜层至少有一颗竹结构。 至少一个颗粒具有基本上一个取向。

公开(公告)号：US06335273B2

公开(公告)日：2002-01-01

申请号：US09443376

申请日：1999-11-19

申请人： Richard J. Huang ,  Guarionex Morales ,  Simon Chan

发明人： Richard J. Huang ,  Guarionex Morales ,  Simon Chan

IPC分类号： H01L214763

CPC分类号： H01L21/02131 ,  H01L21/0214 ,  H01L21/02274 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/31629 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S257/915 ,  H01L2924/00

摘要： A method for using low dielective SiOF in a process to manufacture semiconductor products, comprising the steps of: obtaining a layer of SiOF; and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing hydrogen. It is further preferred that the treated surface be passivated. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielective layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.

摘要翻译： 一种在制造半导体产品的方法中使用低选择性SiOF的方法，包括以下步骤：获得SiOF层; 并从SiOF层的表面上消耗氟。 在优选的实施方案中，耗尽步骤包括用含有氢的等离子体处理SiOF层的表面的步骤。 进一步优选的是，处理过的表面被钝化。 本发明还包括一种半导体芯片，其包括具有至少第一和第二层的集成电路，以及设置在层之间的SiOF的半导体层，其中所述SiOF半导体层包括其一个边缘处的第一区域，该第一区域耗尽氟 到预定深度。

公开(公告)号：US6060380A

公开(公告)日：2000-05-09

申请号：US187391

申请日：1998-11-06

申请人： Ramkumar Subramanian ,  Bhanwar Singh ,  Simon Chan ,  Fei Wang

发明人： Ramkumar Subramanian ,  Bhanwar Singh ,  Simon Chan ,  Fei Wang

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76811 ,  H01L21/31144 ,  H01L21/76813

摘要： A method for etching openings in an integrated circuit uses siliconoxynitride as a hardmask layer. Because of the relatively low reflectivity of siliconoxynitride, when a photoresist layer is deposited on the siliconoxynitride hardmask layer and is exposed to light, the photoresist layer is patterned more conformingly to a desired pattern. The present invention may be used to particular advantage for etching contiguous trench lines and via holes in a dual damascene etch process for small dimension integrated circuits.

摘要翻译： 用于蚀刻集成电路中的开口的方法使用硅氧氮化物作为硬掩模层。 由于硅氧氮化物的相对低的反射率，当光致抗蚀剂层沉积在硅氧氮化物硬掩模层上并暴露于光时，光致抗蚀剂层被图案更符合期望的图案。 本发明可以用于在用于小尺寸集成电路的双镶嵌蚀刻工艺中蚀刻连续沟槽线和通孔的特别优点。

公开(公告)号：US09185793B2

公开(公告)日：2015-11-10

申请号：US13483185

申请日：2012-05-30

申请人： Dror Hurwitz ,  Simon Chan ,  Alex Huang

发明人： Dror Hurwitz ,  Simon Chan ,  Alex Huang

IPC分类号： H05K1/11 ,  H05K1/02 ,  H01L23/498 ,  H05K3/46

CPC分类号： H05K1/0222 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/4647 ,  H05K3/4682 ,  H05K2201/10378 ,  H05K2203/0384 ,  Y10T29/49155 ,  H01L2924/00012 ,  H01L2924/00

摘要： A multilayer electronic structure comprising a plurality of dielectric layers extending in an X-Y plane and comprising at least one coaxial pair of stacked posts extending through at least one dielectric layer in a Z direction that is substantially perpendicular to the X-Y plane, wherein the coaxial pair of stacked via posts comprises a central post surrounded by a torroidal via post separated from the central post by a separating tube of dielectric material.

摘要翻译： 一种多层电子结构，包括在XY平面中延伸的多个电介质层，并且包括至少一对同轴对堆叠的柱，其延伸穿过基本上垂直于XY平面的Z方向上的至少一个电介质层，其中同轴对 堆叠的通孔支柱包括中心柱，其由与介电材料的分离管与中心柱分离的环形通孔柱包围。

公开(公告)号：US20080161122A1

公开(公告)日：2008-07-03

申请号：US11579597

申请日：2005-05-09

申请人： Ashley Smith ,  Simon Chan

发明人： Ashley Smith ,  Simon Chan

IPC分类号： A63B53/04 ,  A63B53/02

CPC分类号： A63B53/0487 ,  A63B53/02 ,  A63B60/00 ,  A63B2053/0441

摘要： A putter-type golf club comprising an alignment system and a club head assembly. The putter-type club head has a body that is preferably composed of aluminium, with a rear weight disc and small inserts composed of a material denser than the material used for the remainder of the club head (excluding inserts in the “wings” on the club head and/or the neck of the club). The body has an alignment channel that is approximately the same width as a standard golf ball, and which runs from the face to the rear of the club head. In a preferred embodiment this alignment channel is black or dark in colour with a white or light-coloured border. The putter-type club has a neck that is inserted laterally through the side of the club head, such that it runs parallel to the face of the club head and for substantially the length of the face.

摘要翻译： 一种推杆式高尔夫球杆，包括对准系统和球杆头组件。 推杆式球杆头具有优选地由铝组成的主体，其具有后配重盘和小型插入件，其由比俱乐部头部剩余部分中使用的材料更密集的材料（不包括在“ 球杆头和/或俱乐部的脖子）。 身体具有与标准高尔夫球大致相同的宽度的对准通道，并且从球杆头的表面延伸到后部。 在优选实施例中，该对准通道为黑色或深色，具有白色或浅色边框。 推杆式球杆具有横向穿过球杆头侧面的颈部，使得其平行于球杆头的表面延伸并且基本上延伸到面部的长度。

公开(公告)号：US07048316B1

公开(公告)日：2006-05-23

申请号：US10194529

申请日：2002-07-12

申请人： Richard Blank ,  Simon Chan ,  Edmund Minshall ,  Peter Woytowitz

发明人： Richard Blank ,  Simon Chan ,  Edmund Minshall ,  Peter Woytowitz

IPC分类号： B66C1/00

CPC分类号： H01L21/68707 ,  H01L21/67748 ,  Y10S294/902 ,  Y10S414/135 ,  Y10S414/141

摘要： This invention provides a method and a support device for a wafer transfer process which has a first vertical, second horizontal and third compound angled surfaces, as well as a pair of sidewalls all contiguously connected to one another. The third surface has at least two angled receiving surfaces whereby one of such angled receiving surfaces has a small angle of incline for initially receiving and delivering a wafer. The other angled receiving surface has a steep angle of incline for effectively receiving, holding and transporting a semiconductor wafer by increasing an effective coefficient of friction of the wafer to provide a secure resting point for such wafer during a transfer process while simultaneously increasing the speed thereof. Furthermore, a hole may be provided in the support device for attaching the support device, or a plurality of support devices having holes, to an end-effector.

摘要翻译： 本发明提供了一种用于晶片转移过程的方法和支持装置，其具有第一垂直，第二水平和第三复合物的倾斜表面，以及一对彼此连续地连接的侧壁。 第三表面具有至少两个成角度的接收表面，由此这种成角度的接收表面中的一个具有小的倾斜角度，用于初始接收和传送晶片。 另一个倾斜的接收表面具有陡峭的倾斜角，用于通过增加晶片的有效摩擦系数来有效地接收，保持和传输半导体晶片，以在转移过程中为这种晶片提供安全的静止点，同时增加其速度 。 此外，可以在支撑装置中设置孔，用于将支撑装置或具有孔的多个支撑装置附接到端部执行器。

公开(公告)号：US20060006552A1

公开(公告)日：2006-01-12

申请号：US10887585

申请日：2004-07-08

申请人： Inkuk Kang ,  Hiroyuki Kinoshita ,  Boon-Yong Ang ,  Hajime Wada ,  Simon Chan ,  Cinti Chen

发明人： Inkuk Kang ,  Hiroyuki Kinoshita ,  Boon-Yong Ang ,  Hajime Wada ,  Simon Chan ,  Cinti Chen

IPC分类号： H01L23/48

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/05181 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05042

摘要： According to one exemplary embodiment, a structure in a semiconductor die comprises a metal pad situated in an interconnect metal layer, where the metal pad comprises copper. The structure further comprises an interlayer dielectric layer situated over the metal pad. The structure further comprises a terminal via defined in the interlayer dielectric layer, where the terminal via is situated on the metal pad. The terminal via extends along only one side of the metal pad. The structure further comprises a terminal metal layer situated on the interlayer dielectric layer and in the terminal via. The structure further comprises a dielectric liner situated on the terminal metal layer, where a bond pad opening is defined in the dielectric liner, and where the bond pad opening exposes a portion of the terminal metal layer. The interlayer dielectric layer is situated between the exposed portion of the terminal metal layer and metal pad.

摘要翻译： 根据一个示例性实施例，半导体管芯中的结构包括位于互连金属层中的金属焊盘，其中金属焊盘包括铜。 该结构还包括位于金属焊盘上的层间电介质层。 该结构还包括限定在层间电介质层中的端子通孔，其中端子通孔位于金属焊盘上。 端子通孔仅沿着金属焊盘的一侧延伸。 该结构还包括位于层间电介质层和端子通孔中的端子金属层。 所述结构还包括位于所述端子金属层上的电介质衬垫，其中所述电介质衬垫中限定了焊盘开口，并且所述接合焊盘开口露出所述端子金属层的一部分。 层间绝缘层位于端子金属层的暴露部分和金属焊盘之间。

公开(公告)号：US09161461B2

公开(公告)日：2015-10-13

申请号：US13523116

申请日：2012-06-14

申请人： Dror Hurwitz ,  Simon Chan ,  Alex Huang

发明人： Dror Hurwitz ,  Simon Chan ,  Alex Huang

IPC分类号： H05K1/02 ,  H05K3/10 ,  H05K3/46 ,  H01L23/367 ,  H01L23/498 ,  H01L21/48

CPC分类号： H05K3/4697 ,  H01L21/4857 ,  H01L23/3677 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2203/308 ,  Y10T29/49155 ,  H01L2924/00

摘要： A multilayer electronic structure comprising a plurality of layers extending in an X-Y plane consisting of a dielectric material surrounding metal via posts that conduct in a Z direction perpendicular to the X-Y plane, wherein at least one multilayered hole crosses at least two layers of the plurality of layers and comprises at least two hole layers in adjacent layers of the multilayer composite electronic structure, wherein the at least two holes in adjacent layers have different dimensions in the X-Y plane, such that a perimeter of the multilayered hole is stepped and where at least one hole is an aperture to a surface of the multilayer electronic structure.

摘要翻译： 一种多层电子结构，包括在XY平面中延伸的多个层，所述多个层由围绕金属通孔的介电材料构成，所述介电材料围绕垂直于所述XY平面的Z方向传导，其中至少一个多层孔穿过所述多个 层，并且在多层复合电子结构的相邻层中包括至少两个孔层，其中相邻层中的至少两个孔在XY平面中具有不同的尺寸，使得多层孔的周边是阶梯状的，并且其中至少一个 孔是多层电子结构的表面的孔。