Integrated circuit system employing stress-engineered spacers
    11.
    发明授权
    Integrated circuit system employing stress-engineered spacers 有权
    采用应力工程间隔件的集成电路系统

    公开(公告)号:US08338245B2

    公开(公告)日:2012-12-25

    申请号:US12048994

    申请日:2008-03-14

    IPC分类号: H01L21/8238

    摘要: An integrated circuit system that includes: providing a substrate including a first region with a first device and a second device and a second region with a resistance device; configuring the first device, the second device, and the resistance device to include a first spacer and a second spacer; forming a stress inducing layer over the first region and the second region; processing at least a portion of the stress inducing layer formed over the first region to alter the stress within the stress inducing layer; and forming a third spacer adjacent the second spacer of the first device and the second device from the stress inducing layer.

    摘要翻译: 一种集成电路系统,包括:提供包括具有第一装置的第一区域的基板和具有电阻装置的第二区域; 配置第一装置,第二装置和电阻装置以包括第一间隔件和第二间隔件; 在所述第一区域和所述第二区域上形成应力诱导层; 处理形成在第一区域上的应力诱导层的至少一部分,以改变应力诱导层内的应力; 以及从所述应力诱导层形成邻近所述第一器件和所述第二器件的第二间隔物的第三间隔物。

    FinFET with novel body contact for multiple Vt applications
    12.
    发明申请
    FinFET with novel body contact for multiple Vt applications 有权
    FinFET具有新的身体接触,适用于多种Vt应用

    公开(公告)号:US20120007180A1

    公开(公告)日:2012-01-12

    申请号:US12803776

    申请日:2010-07-06

    IPC分类号: H01L27/12 H01L21/84

    CPC分类号: H01L29/785 H01L29/66795

    摘要: FinFET devices are formed with body contact structures enabling the fabrication of such devices having different gate threshold voltages (Vt). A body contact layer is formed to contact the gate electrode (contact) enabling a forward body bias and a reduction in Vt. Two example methods of fabrication (and resulting structures) are provided. In one method, the gate electrode (silicon-based) and body contact layer (silicon) are connected by growing epitaxy which merges the two structures forming electrical contact. In another method, a via is formed that intersects with the gate electrode (suitable conductive material) and body contact layer and is filled with conductive material to electrically connect the two structures. As a result, various FinFETs with different Vt can be fabricated for different applications.

    摘要翻译: FinFET器件形成有能够制造具有不同栅极阈值电压(Vt)的这种器件的体接触结构。 形成身体接触层以接触栅电极(接触),从而能够实现正向偏置和Vt的减小。提供了两种制造方法(和结果)。 在一种方法中,栅电极(硅基)和体接触层(硅)通过生长的外延连接,该外延合并形成电接触的两个结构。 在另一种方法中,形成与栅电极(合适的导电材料)和体接触层相交的通孔,并且填充有导电材料以电连接两个结构。 因此,可以为不同的应用制造具有不同Vt的各种FinFET。

    Method to tune narrow width effect with raised S/D structure
    16.
    发明授权
    Method to tune narrow width effect with raised S/D structure 有权
    用提高的S / D结构调整窄宽度效应的方法

    公开(公告)号:US08785287B2

    公开(公告)日:2014-07-22

    申请号:US12803754

    申请日:2010-07-06

    IPC分类号: H01L21/336 H01L21/265

    摘要: A method (and semiconductor device) of fabricating a semiconductor device adjusts gate threshold (Vt) of a field effect transistor (FET) with raised source/drain (S/D) regions. A halo region is formed in a two-step process that includes implanting dopants using conventional implantation techniques and implanting dopants at a specific twist angle. The dopant concentration in the halo region near the active edge of the raised S/D regions is higher and extends deeper than the dopant concentration within the interior region of the raised S/D regions. As a result, Vt near the active edge region is adjusted and different from the Vt at the active center regions, thereby achieving same or similar Vt for a FET with different width.

    摘要翻译: 制造半导体器件的方法(和半导体器件)调节具有升高的源极/漏极(S / D)区域的场效应晶体管(FET)的栅极阈值(Vt)。 以包括使用常规植入技术注入掺杂剂并以特定扭转角注入掺杂剂的两步工艺形成晕圈区域。 在升高的S / D区域的有源边缘附近的卤素区域中的掺杂剂浓度更高并且比在凸起的S / D区域的内部区域内的掺杂剂浓度更深。 结果,有源边缘区域附近的Vt被调节并且与有源中心区域处的Vt不同,从而为具有不同宽度的FET获得相同或相似的Vt。

    LDMOS with improved breakdown voltage
    17.
    发明授权
    LDMOS with improved breakdown voltage 有权
    LDMOS具有改善的击穿电压

    公开(公告)号:US08748271B2

    公开(公告)日:2014-06-10

    申请号:US13046313

    申请日:2011-03-11

    摘要: An LDMOS is formed with a field plate over the n− drift region, coplanar with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second coplanar gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack of a high-k metal gate and the second gate stack of a field plate on a gate oxide layer, forming the first and second gate stacks with different gate electrode materials on a common gate oxide, and forming the gate stacks separated from each other and with different gate dielectric materials.

    摘要翻译: LDMOS在n-漂移区上形成有与栅叠层共面的场板,并且具有比栅叠层更高的功函数。 实施例包括形成第一导电类型的阱,具有由第二导电类型阱包围的源,在衬底中具有漏极,在衬底上在第一阱的一部分上形成第一和第二共面栅叠层, 分别调整第一和第二栅极堆叠的功函数,以获得第二栅极堆叠的较高功函数。 其他实施例包括在栅极氧化物层上形成高k金属栅极的第一栅极堆叠和场板的第二栅极堆叠,在公共栅极氧化物上形成具有不同栅电极材料的第一和第二栅极堆叠,以及形成 栅极堆叠彼此分离并具有不同的栅极电介质材料。