公开(公告)号：US08612814B1

公开(公告)日：2013-12-17

申请号：US12814713

申请日：2010-06-14

申请人： Jun Pin Tan ,  Kiun Kiet Jong ,  Boon Jin Ang

发明人： Jun Pin Tan ,  Kiun Kiet Jong ,  Boon Jin Ang

IPC分类号： G01R31/28

CPC分类号： G11C29/44 ,  G11C11/41 ,  G11C29/40 ,  G11C29/52 ,  G11C2029/0409

摘要： Integrated circuits with error detection circuitry are provided. Integrated circuits may include memory cells organized into frames. The error detection circuitry may compress each frame to scan for soft errors. The error detection circuitry may include multiple input shift registers (MISRs), a data register, and a signature comparator. The data frames may be read, compressed, and shifted into the MISRs in parallel. After all the data frames have been read, the MISRs may provide a scanned MISR signature at their outputs. Computer-aided design (CAD) tools may be used to calculate a precomputed MISR signature. The precomputed MISR signature may be loaded into the data register. The signature comparator compares the scanned MISR signature with the precomputed MISR signature. If the signatures match, then the device is free of soft errors. If the signatures do not match, then at least one soft error exists.

摘要翻译： 提供了具有错误检测电路的集成电路。 集成电路可以包括被组织成帧的存储器单元。 错误检测电路可以压缩每个帧以扫描软错误。 错误检测电路可以包括多个输入移位寄存器（MISR），数据寄存器和签名比较器。 数据帧可以被并行读取，压缩和移入MISR中。 在读取所有数据帧之后，MISR可以在其输出端提供扫描的MISR签名。 计算机辅助设计（CAD）工具可用于计算预计算的MISR签名。 预计算的MISR签名可以加载到数据寄存器中。 签名比较器将扫描的MISR签名与预先计算的MISR签名进行比较。 如果签名匹配，则设备没有软错误。 如果签名不匹配，则至少存在一个软错误。

公开(公告)号：US07787314B2

公开(公告)日：2010-08-31

申请号：US12208967

申请日：2008-09-11

申请人： Jun Pin Tan ,  Wei Yee Koay ,  Boon Jin Ang ,  Choong Kit Wong ,  Guang Sheng Soh

发明人： Jun Pin Tan ,  Wei Yee Koay ,  Boon Jin Ang ,  Choong Kit Wong ,  Guang Sheng Soh

IPC分类号： G11C7/10

CPC分类号： H03K19/1735 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  H03K5/133

摘要： In mask programmable integrated circuit, such as a structured ASIC, a delay chain provides a delay that is set by a mask programmable switch. The delay chain receives an input to allow the delay mask programmed delay to be overridden using a JTAG controller. This allows testing of different delays. The input may also be provided by a fuse block, so that the fuse block can override the mask programmable switch, thus allowing a delay to be changes after mask programming.

摘要翻译： 在掩模可编程集成电路（例如结构化ASIC）中，延迟链提供由掩模可编程开关设置的延迟。 延迟链接收输入以允许使用JTAG控制器覆盖延迟掩码编程的延迟。 这允许测试不同的延迟。 输入也可以由熔丝块提供，使得熔丝块可以覆盖掩模可编程开关，从而允许在掩模编程之后改变延迟。

公开(公告)号：US07565390B1

公开(公告)日：2009-07-21

申请号：US11089684

申请日：2005-03-23

申请人： Tat Mun Lui ,  Bee Yee Ng ,  Jun Pin Tan ,  Boon Jin Ang

发明人： Tat Mun Lui ,  Bee Yee Ng ,  Jun Pin Tan ,  Boon Jin Ang

IPC分类号： G06F7/48

CPC分类号： G06F7/5443 ,  G06F7/4991 ,  H03K19/17704 ,  H03K19/17732

摘要： In circuitry such as a programmable logic device (“PLD”), each of several multiplier blocks includes partial products generation circuitry and partial products addition circuitry. Two such multiplier blocks can be used together to provide multiply-accumulate (“MAC”) capability. The partial products addition circuitry in one of the paired blocks is used to add each successive product produced by the other paired block to a previous accumulation of products in the first-mentioned paired block. Provisions are also made for accumulating any overflow from operation of the partial products addition circuitry in the first-mentioned paired block.

摘要翻译： 在诸如可编程逻辑器件（“PLD”）的电路中，几个乘法器块中的每一个包括部分乘积生成电路和部分乘积加法电路。 两个这样的乘法器块可以一起使用以提供乘法累加（“MAC”）能力。 一个配对块中的部分乘积加法电路用于将由另一个配对块产生的每个连续乘积加到先前提到的配对块中先前积累的乘积。 还提供了在第一提到的配对块中累积部分产品添加电路的操作的任何溢出的规定。

公开(公告)号：US08400863B1

公开(公告)日：2013-03-19

申请号：US12860734

申请日：2010-08-20

申请人： Zun Yang Tan ,  Wei Yee Koay ,  Boon Jin Ang ,  Tat Mun Lui ,  Eu Geen Chew

发明人： Zun Yang Tan ,  Wei Yee Koay ,  Boon Jin Ang ,  Tat Mun Lui ,  Eu Geen Chew

IPC分类号： G11C8/00

CPC分类号： G11C8/12

摘要： Circuits for a memory array and a method of operating a configurable memory block are disclosed. An embodiment of the disclosed memory circuits includes a first memory block coupled to a second memory block to form an array of memory blocks. Each of the memory blocks has multiple bit lines with a dedicated address decoder coupled to the bit lines from each of the memory blocks. Switches are placed in between the first and second memory blocks such that each of the bit lines from the first memory block is connected to a corresponding bitline from the second memory block through one of the switches. The switches may be used to either connect the second memory block to the first memory block or disconnect the second memory block from the first memory block.

摘要翻译： 公开了用于存储器阵列的电路和操作可配置存储器块的方法。 所公开的存储器电路的实施例包括耦合到第二存储器块以形成存储器块阵列的第一存储器块。 每个存储器块具有多个位线，其中专用地址解码器耦合到来自每个存储器块的位线。 开关被放置在第一和第二存储器块之间，使得来自第一存储器块的每个位线通过其中一个开关连接到来自第二存储器块的相应位线。 交换机可以用于将第二存储器块连接到第一存储器块或将第二存储器块与第一存储器块断开。

公开(公告)号：US07242218B2

公开(公告)日：2007-07-10

申请号：US11003586

申请日：2004-12-02

申请人： Rafael Camarota ,  Irfan Rahim ,  Boon Jin Ang ,  Thow Pang Chong

发明人： Rafael Camarota ,  Irfan Rahim ,  Boon Jin Ang ,  Thow Pang Chong

IPC分类号： H03K19/173 ,  H03K19/177 ,  G06F7/38 ,  H01L25/00

CPC分类号： G06F15/7867 ,  H03K19/17732 ,  H03K19/1776 ,  H03K19/17768 ,  H03K19/17772 ,  H03K19/17776

摘要： Techniques for combining volatile and non-volatile programmable logic into one integrated circuit (IC) are provided. An IC is segregated into two portions. A first block of programmable logic is configured by bits stored in on-chip non-volatile memory. A second block of programmable logic is configured by bits stored in off-chip memory. The function of IO banks on the IC is multiplexed between the two logic blocks of the IC. The programmable logic in the first block can be configured and fully functional in a fraction of the time that the programmable logic in the second block can be configured. The programmable logic in the first block can configure fast enough and have enough independence to assist in the configuration of the second block. The non-volatile memory can also provide security features to a user design, such as encryption.

摘要翻译： 提供了将易失性和非易失性可编程逻辑组合到一个集成电路（IC）中的技术。 IC分为两部分。 可编程逻辑的第一块由存储在片上非易失性存储器中的位来配置。 可编程逻辑的第二块由存储在片外存储器中的位配置。 IC上的IO组的功能在IC的两个逻辑块之间复用。 第一块中的可编程逻辑可以在可配置第二块中的可编程逻辑的几分之一时间内配置和完全运行。 第一块中的可编程逻辑可以配置得足够快，并具有足够的独立性来辅助第二块的配置。 非易失性存储器还可以为诸如加密的用户设计提供安全特征。

公开(公告)号：US06489817B1

公开(公告)日：2002-12-03

申请号：US09965290

申请日：2001-09-26

申请人： Choong Kit Wong ,  Sammy Cheung ,  Boon Jin Ang

发明人： Choong Kit Wong ,  Sammy Cheung ,  Boon Jin Ang

IPC分类号： H03K2100

CPC分类号： H03K23/68

摘要： A clock divider is described. The clock divider includes: a positive edge triggered state machine having a first input for receiving a first input signal and a first output for providing a first output signal; a negative edge triggered state machine having a second input for receiving a second input signal and a second output for providing a second output signal; and a first combination logic coupled to the positive edge triggered state machine and the negative edge triggered state machine, the first combination logic having a third input for receiving third input signals and a third output for providing a third output signal, where (1) at least one of the first input signal and the second input signal includes an input clock signal having an input clock signal period, (2) the third input signals include the first output signal and the second output signal, and (3) the third output includes an output clock signal having an output clock signal period, where the output clock signal period is a multiple of the input clock signal period.

摘要翻译： 描述了时钟分频器。 时钟分频器包括：正沿触发状态机，具有用于接收第一输入信号的第一输入端和用于提供第一输出信号的第一输出端; 负边缘触发状态机，具有用于接收第二输入信号的第二输入和用于提供第二输出信号的第二输出; 以及耦合到所述正沿触发状态机和所述负沿触发状态机的第一组合逻辑，所述第一组合逻辑具有用于接收第三输入信号的第三输入和用于提供第三输出信号的第三输出，其中（1） 第一输入信号和第二输入信号中的至少一个包括具有输入时钟信号周期的输入时钟信号，（2）第三输入信号包括第一输出信号和第二输出信号，以及（3）第三输出包括 具有输出时钟信号周期的输出时钟信号，其中输出时钟信号周期是输入时钟信号周期的倍数。

公开(公告)号：US08659334B2

公开(公告)日：2014-02-25

申请号：US13543724

申请日：2012-07-06

申请人： Teik Wah Lim ,  Eng Huat Lee ,  Ie Chen Chia ,  Thow Pang Chong ,  Boon Jin Ang ,  Kim Pin Tan

发明人： Teik Wah Lim ,  Eng Huat Lee ,  Ie Chen Chia ,  Thow Pang Chong ,  Boon Jin Ang ,  Kim Pin Tan

IPC分类号： H03L7/06

CPC分类号： H03L7/081 ,  G11C17/16 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/4402 ,  H03L7/08

摘要： Circuits and a method for tuning an integrated circuit (IC) are disclosed. The IC includes multiple programmable fuses coupled to a control block. The programmable fuses used may be one-time programmable (OTP) fuses. The control block reads settings or data stored in the programmable fuses. A tuning circuit coupled to the control block receives the delay transmitted by the control block. The tuning circuit allows tuning of the IC without changes to the fabrication mask. The tuning circuit may include delay chains to provide additional delay to the IC when needed and the delay in the tuning circuit is configured based on the delay value stored in the programmable fuses and transmitted by the control block.

摘要翻译： 公开了用于调谐集成电路（IC）的电路和方法。 IC包括耦合到控制块的多个可编程熔丝。 所使用的可编程保险丝可能是一次性可编程（OTP）保险丝。 控制块读取存储在可编程保险丝中的设置或数据。 耦合到控制块的调谐电路接收由控制块发送的延迟。 调谐电路允许调节IC而不改变制造掩模。 调谐电路可以包括延迟链，以在需要时向IC提供额外的延迟，并且基于存储在可编程保险丝中并由控制块传输的延迟值来配置调谐电路中的延迟。

公开(公告)号：US07218141B2

公开(公告)日：2007-05-15

申请号：US11007827

申请日：2004-12-07

申请人： Bee Yee Ng ,  Boon Jin Ang

发明人： Bee Yee Ng ,  Boon Jin Ang

IPC分类号： G06F7/38 ,  H03K19/173 ,  H03K19/177 ,  H01L25/00

CPC分类号： H03K19/17744

摘要： Techniques are provided for improving signal timing characteristics of differential input/output (IO) circuits on programmable logic integrated circuits. A differential buffer receives differential signals applied to differential input pins. The output signals of the differential buffer are routed to two hard IO decoder blocks that are located in two adjacent rows/columns of programmable logic elements. Each IO decoder block has a data-in register that receives output signals of the differential buffer. The data-in registers in two adjacent IO decoder blocks support a double clocking technique. IO decoder blocks of the present invention have reduced setup times, hold times, and sampling windows relative to soft DDIO blocks, and have a minimal impact on die area.

摘要翻译： 提供了用于改善可编程逻辑集成电路上的差分输入/输出（IO）电路的信号定时特性的技术。 差分缓冲器接收施加到差分输入引脚的差分信号。 差分缓冲器的输出信号被路由到位于可编程逻辑元件的两个相邻行/列中的两个硬IO解码器块。 每个IO解码器块具有接收差分缓冲器的输出信号的数据输入寄存器。 两个相邻IO解码器块中的数据输入寄存器支持双时钟技术。 本发明的IO解码器块相对于软DDIO块具有减少的建立时间，保持时间和采样窗口，并且对芯片面积的影响最小。

公开(公告)号：US06988258B2

公开(公告)日：2006-01-17

申请号：US10316237

申请日：2002-12-09

申请人： Kim Pin Tan ,  Boon Jin Ang ,  Bee Yee Ng

发明人： Kim Pin Tan ,  Boon Jin Ang ,  Bee Yee Ng

IPC分类号： G06F17/50

CPC分类号： H03K19/1735

摘要： A mask-programmable logic device includes logical building blocks that can be connected together to form various logical units for programmable logic. Functionality of a comparable conventional programmable logic device can be provided with fewer gates in this way than by providing all of the gates normally present on that comparable conventional programmable logic device, resulting in fewer unused gates in the devices once mask-programmed.

摘要翻译： 掩模可编程逻辑器件包括可以连接在一起以形成用于可编程逻辑的各种逻辑单元的逻辑构建块。 可以以这种方式提供具有较少的门的功能，而不是通过提供通常存在于该可比较的常规可编程逻辑器件上的所有门，从而在屏蔽编程中导致器件中较少的未使用的栅极。

公开(公告)号：US08739099B1

公开(公告)日：2014-05-27

申请号：US12176379

申请日：2008-07-20

申请人： Victor R. Maruri ,  Boon Jin Ang ,  Henry Y. Lui ,  Surinder Singh ,  Thow Pang Chong ,  Tony K. Ngai

发明人： Victor R. Maruri ,  Boon Jin Ang ,  Henry Y. Lui ,  Surinder Singh ,  Thow Pang Chong ,  Tony K. Ngai

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5031 ,  G06F2217/62

摘要： A method for determining clock uncertainties is provided. The method includes identifying clock transfer types between registers from an integrated circuit design and identifying contributors to the clock uncertainties for each of the clock transfers. The jitter associated with each identified contributor is calculated for both set-up time and hold time. This calculated jitter is incorporated into a slack calculation to determine whether timing constraints are met for a circuit design.

摘要翻译： 提供了一种确定时钟不确定度的方法。 该方法包括从集成电路设计中识别寄存器之间的时钟传输类型，并且识别每个时钟传输的时钟不确定性的贡献者。 针对建立时间和保持时间计算与每个识别的贡献者相关联的抖动。 该计算的抖动被并入到松弛计算中以确定电路设计是否满足时序约束。