公开(公告)号：US20220085045A1

公开(公告)日：2022-03-17

申请号：US17202900

申请日：2021-03-16

Applicant: KIOXIA CORPORATION

Inventor： Satoshi NAGASHIMA ,  Fumitaka ARAI

IPC: H01L27/11565 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11582

Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, and at least one memory structure. The first conductive layer includes a first portion, a second portion, and a third portion, a fourth portion, and a fifth portion. The first portion is provided between the second portion and the third portion in a second direction. The second conductive layer includes a sixth portion, a seventh portion, and an eighth portion, a ninth portion, and a tenth portion. The sixth portion is provided between the seventh portion and the eighth portion in the second direction. The second portion is provided between the sixth portion and the eighth portion in the second direction.

公开(公告)号：US20250016976A1

公开(公告)日：2025-01-09

申请号：US18887835

申请日：2024-09-17

Applicant: Kioxia Corporation

Inventor： Teruhisa SONOHARA ,  Shunichi SENO ,  Hiroki TOKUHIRA ,  Fumitaka ARAI

IPC: H10B12/00 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4096 ,  H01L21/02 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor memory device includes: a first wiring; a first semiconductor layer connected to the first wiring, the first semiconductor layer; a first electrode, the first electrode being connected to the first semiconductor layer; a second electrode disposed between the first electrode and the first wiring, the second electrode being opposed to the first semiconductor layer; a third electrode disposed between the second electrode and the first wiring, the third electrode; a second semiconductor layer disposed between the third electrode and the first semiconductor layer, the second semiconductor layer being opposed to the third electrode; and an electric charge accumulating layer electrically connected to the first wiring via the second semiconductor layer, the electric charge accumulating layer being opposed to the first semiconductor layer.

公开(公告)号：US20240188307A1

公开(公告)日：2024-06-06

申请号：US18441204

申请日：2024-02-14

Applicant: Kioxia Corporation

Inventor： Masahiro KIYOTOSHI ,  Akihito YAMAMOTO ,  Yoshio OZAWA ,  Fumitaka ARAI ,  Riichiro SHIROTA

IPC: H10B63/00 ,  H01L21/02 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/762 ,  H01L27/105 ,  H01L29/51 ,  H10B43/27 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40 ,  H10B69/00 ,  H10B99/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/845 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/30604 ,  H01L21/31055 ,  H01L21/3212 ,  H01L21/32136 ,  H01L21/762 ,  H01L27/105 ,  H01L29/40117 ,  H01L29/513 ,  H01L29/518 ,  H10B43/27 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40 ,  H10B63/00 ,  H10B63/20 ,  H10B63/30 ,  H10B69/00 ,  H10B99/00 ,  H10N70/021 ,  H10N70/231 ,  H10N70/801 ,  H10N70/882 ,  H10N70/028 ,  H10N70/20 ,  H10N70/823 ,  H10N70/8413 ,  H10N70/8828 ,  H10N70/8833

Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.

公开(公告)号：US20220130754A1

公开(公告)日：2022-04-28

申请号：US17438728

申请日：2019-03-19

Applicant: Kioxia Corporation

Inventor： Keisuke NAKATSUKA ,  Yasuhito YOSHIMIZU ,  Tomoya SANUKI ,  Fumitaka ARAI

IPC: H01L23/522 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor memory device including: plural first conductive layers stacked on a substrate; plural second conductive layers each stacked between the first conductive layers; a pillar that extends in a stacking direction of the first and second conductive layers and forms plural memory cells at intersections of the first and second conductive layers in a region where first and second conductive layers are arranged; a first contact plug that extends in the stacking direction of the first and second conductive layers and is connected to the first conductive layers in the region where the first and second conductive layers are arranged; and a second contact plug that extends in the stacking direction of the first and second conductive layers and is connected to the second conductive layers in the region where the first conductive layers and second conductive layers are arranged.