公开(公告)号：US12058862B2

公开(公告)日：2024-08-06

申请号：US18091728

申请日：2022-12-30

Applicant: KIOXIA CORPORATION

Inventor： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi

IPC: H10B43/27 ,  G11C16/04 ,  H01L29/51 ,  H10B41/27 ,  H10B43/20 ,  H10B43/40 ,  H10B43/50 ,  H10B99/00 ,  H10B41/20

CPC classification number: H10B43/27 ,  G11C16/0483 ,  H01L29/513 ,  H10B41/27 ,  H10B43/20 ,  H10B43/40 ,  H10B43/50 ,  H10B99/00 ,  H10B41/20

Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.

公开(公告)号：US11903207B2

公开(公告)日：2024-02-13

申请号：US17750207

申请日：2022-05-20

Applicant: Kioxia Corporation

Inventor： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

IPC: H10B43/27 ,  H01L21/822 ,  H01L27/06 ,  H01L27/105 ,  H10B41/27 ,  H10B43/20 ,  H10B43/40 ,  H10B69/00 ,  G11C16/04

CPC classification number: H10B43/27 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H10B41/27 ,  H10B43/20 ,  H10B43/40 ,  H10B69/00 ,  G11C16/0483

Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

公开(公告)号：US11362106B2

公开(公告)日：2022-06-14

申请号：US17141504

申请日：2021-01-05

Applicant: Kioxia Corporation

Inventor： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

IPC: H01L27/105 ,  H01L27/11582 ,  H01L21/822 ,  H01L27/06 ,  H01L27/115 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11556 ,  G11C16/04

Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

公开(公告)号：US11871576B2

公开(公告)日：2024-01-09

申请号：US17113285

申请日：2020-12-07

Applicant: Kioxia Corporation

Inventor： Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Mie Matsuo ,  Kenichiro Yoshii ,  Koichiro Shindo ,  Kazushige Kawasaki ,  Tomoya Sanuki

IPC: H10B43/40 ,  H01L25/065 ,  H01L25/18 ,  H10B43/27 ,  H10B43/30 ,  H10B43/50 ,  H01L21/18 ,  H01L21/768 ,  H01L23/00

CPC classification number: H10B43/40 ,  H01L21/185 ,  H01L21/76898 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H10B43/27 ,  H10B43/30 ,  H10B43/50 ,  H01L2224/08145

Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.

公开(公告)号：US11792992B2

公开(公告)日：2023-10-17

申请号：US17576164

申请日：2022-01-14

Applicant: Kioxia Corporation

Inventor： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC: H01L29/76 ,  H10B43/27 ,  H01L29/66 ,  H01L29/792 ,  H10B43/20 ,  H01L21/223 ,  H01L21/265 ,  H01L29/78 ,  H01L29/04 ,  H01L29/16 ,  H01L29/423 ,  H01L29/49 ,  H01L29/10

CPC classification number: H10B43/27 ,  H01L21/223 ,  H01L21/265 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/792 ,  H01L29/7926 ,  H10B43/20

Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

公开(公告)号：US11296114B2

公开(公告)日：2022-04-05

申请号：US17335214

申请日：2021-06-01

Applicant: KIOXIA CORPORATION

Inventor： Yoshiaki Fukuzumi ,  Shinya Arai ,  Masaki Tsuji ,  Hideaki Aochi ,  Hiroyasu Tanaka

IPC: H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11575 ,  H01L27/11565 ,  H01L29/423

Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.

公开(公告)号：US11257842B2

公开(公告)日：2022-02-22

申请号：US16849457

申请日：2020-04-15

Applicant: Kioxia Corporation

Inventor： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC: H01L29/76 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11578 ,  H01L21/223 ,  H01L21/265 ,  H01L29/78 ,  H01L29/04 ,  H01L29/16 ,  H01L29/423 ,  H01L29/49 ,  H01L29/10

Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

公开(公告)号：US11594547B2

公开(公告)日：2023-02-28

申请号：US17106414

申请日：2020-11-30

Applicant: Kioxia Corporation

Inventor： Yoshiaki Fukuzumi ,  Hideaki Aochi

IPC: H01L27/11573 ,  H01L27/11582 ,  H01L23/00 ,  H01L25/18 ,  H01L27/11568 ,  H01L21/768 ,  H01L21/18

Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.

公开(公告)号：US11574663B2

公开(公告)日：2023-02-07

申请号：US17109853

申请日：2020-12-02

Applicant: Kioxia Corporation

Inventor： Keisuke Nakatsuka ,  Tomoya Sanuki ,  Takashi Maeda ,  Go Shikata ,  Hideaki Aochi

IPC: G11C7/10 ,  G11C7/08 ,  H01L27/11573 ,  G11C16/26 ,  H01L27/11529 ,  G11C7/18

Abstract: A data latch circuit includes a first n-channel transistor and a first p-channel transistor. A gate of the first n-channel transistor and a gate of the first p-channel transistor are a common gate.

公开(公告)号：US20220173124A1

公开(公告)日：2022-06-02

申请号：US17672819

申请日：2022-02-16

Applicant: Kioxia Corporation

Inventor： Yoshiaki Fukuzumi ,  Shinya Arai ,  Masaki Tsuji ,  Hideaki Aochi ,  Hiroyasu Tanaka

IPC: H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11575 ,  H01L27/11565 ,  H01L29/423

Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.