公开(公告)号：US11923325B2

公开(公告)日：2024-03-05

申请号：US17695654

申请日：2022-03-15

Applicant: Kioxia Corporation

Inventor： Yasuhito Yoshimizu ,  Takashi Fukushima ,  Tatsuro Hitomi ,  Arata Inoue ,  Masayuki Miura ,  Shinichi Kanno ,  Toshio Fujisawa ,  Keisuke Nakatsuka ,  Tomoya Sanuki

IPC: H01L23/00 ,  G06F11/07 ,  H01L23/544

CPC classification number: H01L24/05 ,  G06F11/073 ,  G06F11/0751 ,  H01L23/544 ,  H01L2223/5446 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2924/14511

Abstract: A memory chip unit includes a pad electrode including first and second portions, and a memory cell array. A prober includes a probe card and a movement mechanism. The probe card includes a probe electrode to be in contact with the pad electrode, and a memory controller electrically coupled to the probe electrode and executes reading and writing on the memory cell array. The movement mechanism executes a first operation that brings the probe electrode into contact with the first portion and does not bring the probe electrode into contact with the second portion, and a second operation that does not bring the probe electrode into contact with the first portion and brings the probe electrode into contact with the second portion.

公开(公告)号：US20230307369A1

公开(公告)日：2023-09-28

申请号：US17890377

申请日：2022-08-18

Applicant: Kioxia Corporation

Inventor： Nobuhito Ichiki ,  Keisuke Nakatsuka ,  Shinya Arai ,  Koichi Sakata ,  Susumu Hashimoto

IPC: H01L23/535 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/535 ,  H01L23/53257 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor memory device includes a first wiring, a second wiring, a memory pillar, a semiconductor layer, and a contact plug. The second wiring is provided above the first wiring in a first direction. The memory pillar penetrating at least one of a portion of the first wiring or a portion of the second wiring in the first direction. The semiconductor layer extends in the first direction provided in the memory pillar. The contact plug contains a metal and has a lower surface provided in the memory pillar, and the lower surface is in contact with the semiconductor layer below an upper surface of the second wiring.

公开(公告)号：US11631683B2

公开(公告)日：2023-04-18

申请号：US17011006

申请日：2020-09-03

Applicant: Kioxia Corporation

Inventor： Naoya Yoshimura ,  Keisuke Nakatsuka

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  G11C16/04 ,  H01L27/11556

Abstract: A semiconductor storage device includes first conductive layers stacked in a first direction and extend in a second direction; second conductive layers stacked in the first direction and extend in the second direction; third conductive layers that are electrically connected to the first conductive layers and the second conductive layers and stacked in the first direction; a first insulating layer and a second insulating layer sandwich the first conductive layer; a third insulating layer and a fourth insulating layer sandwich the second conductive layer; first pillars arranged in the second direction in the first insulating layer with a first distance; and second pillars arranged in the second direction in the second insulating layer with the first distance. Each of the second pillars is displaced from a corresponding one of the first pillars by a second distance that is shorter than a half of the first distance in the second direction.

公开(公告)号：US11450611B2

公开(公告)日：2022-09-20

申请号：US17015868

申请日：2020-09-09

Applicant: Kioxia Corporation

Inventor： Tomoya Sanuki ,  Keisuke Nakatsuka ,  Yasuhito Yoshimizu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/535 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L21/768 ,  H01L25/00

Abstract: In one embodiment, a semiconductor device includes a substrate including two element regions that extend in a first direction parallel to a surface of the substrate and are adjacent to each other in a second direction crossing the first direction. The device further includes an interconnection layer provided above the substrate. The device further includes an insulator provided between the substrate and the interconnection layer. The device further includes a plug extending in the second direction and in a third direction crossing the first and second directions in the insulator, provided on each of the element regions, and electrically connected to the element regions and the interconnection layer.

公开(公告)号：US12204765B2

公开(公告)日：2025-01-21

申请号：US18181824

申请日：2023-03-10

Applicant: Kioxia Corporation

Inventor： Tomoya Sanuki ,  Toshio Fujisawa ,  Keisuke Nakatsuka

IPC: G06F12/00 ,  G06F3/06

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor storage device and a memory controller. The nonvolatile semiconductor storage device includes at least one memory device including a plurality of memory cells corresponding to a plurality of pages. The memory controller is configured to control the nonvolatile semiconductor storage device. The pages include a first page. The memory controller is configured to: read first data stored in the first page from the nonvolatile semiconductor storage device; correct a fail bit included in the read first data; generate first spare data including information on the fail bit corrected in the read first data; and store the first spare data in the nonvolatile semiconductor storage device.

公开(公告)号：US12142324B2

公开(公告)日：2024-11-12

申请号：US17681547

申请日：2022-02-25

Applicant: KIOXIA CORPORATION

Inventor： Tomoya Sanuki ,  Keisuke Nakatsuka ,  Daisuke Fujiwara ,  Toshio Fujisawa

IPC: G11C16/08 ,  G11C8/12 ,  G11C16/04 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/34

Abstract: A semiconductor storage device includes a memory cell array and a control circuit. The memory cell array includes a plurality of memory strings, a plurality of word lines, each of which is connected to the memory strings, and a plurality of bit lines connected to the memory strings, respectively. The plurality of bit lines are grouped into a plurality of bit line groups. The control circuit is configured to receive a read command and first address information specifying one or more of the bit line groups. The control circuit is configured to, in response to the read command, read data selectively from each memory string connected to each bit line in the one or more bit line groups specified by the first address information, and output the read data.

公开(公告)号：US12004339B2

公开(公告)日：2024-06-04

申请号：US17643277

申请日：2021-12-08

Applicant: Kioxia Corporation

Inventor： Keisuke Nakatsuka ,  Takuya Ohoka

IPC: H10B12/00

CPC classification number: H10B12/31 ,  H10B12/01 ,  H10B12/50

Abstract: In one embodiment, a semiconductor device includes a substrate, transistors on the substrate, and a stacked film provided above the transistors, including electrode layers separated from each other in a first direction, and including first, second and third regions. The device further includes plugs provided to the electrode layers in the first region, a first columnar portion in the second region, and a second columnar portion in the third region. At least one electrode layer among the electrode layers includes a first portion in the first region, a second portion in the second region, and a third portion in the third region, and is a continuous film from the second portion to the third portion via the first portion. The transistors include first, second and third transistors provided right under the first, second and third regions and electrically connected to first, second and third plugs among the plugs, respectively.

公开(公告)号：US11862246B2

公开(公告)日：2024-01-02

申请号：US17474904

申请日：2021-09-14

Applicant: Kioxia Corporation

Inventor： Tomoya Sanuki ,  Yasuhito Yoshimizu ,  Keisuke Nakatsuka ,  Hideto Horii ,  Takashi Maeda

IPC: G11C16/04 ,  G11C16/30 ,  G11C16/32 ,  G11C5/06 ,  G11C16/26 ,  G11C5/02 ,  G11C16/10 ,  G11C16/08

CPC classification number: G11C16/0433 ,  G11C5/025 ,  G11C5/06 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/102 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32

Abstract: A memory system has a memory cell array having a plurality of strings, the plurality of strings each having a plurality of memory cells connected in series, and a controller configured to perform control of transferring charges to be stored in the plurality of memory cells in the string or transferring charges according to stored data, between potential wells of channels in the plurality of memory cells.