公开(公告)号：US11810624B2

公开(公告)日：2023-11-07

申请号：US17473293

申请日：2021-09-13

Applicant: Kioxia Corporation

Inventor： Koji Kato

IPC: G11C5/02 ,  G11C16/26 ,  G11C16/32 ,  G11C16/10 ,  G11C16/24 ,  G11C16/04 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/32 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor memory device comprises: a substrate; a first conductive layer separated from the substrate in a first direction and extending in a second direction; a second and a third conductive layers separated from the substrate and the first conductive layer in the first direction and aligned in the second direction; a first semiconductor layer facing the first and the second conductive layers; a second semiconductor layer facing the first and the third conductive layers; a first and a second bit lines electrically connected to the first and the second semiconductor layers. At least some of operation parameters in the case of a certain operation being executed on a memory cell corresponding to the first conductive layer differ from at least some of operation parameters in the case of the certain operation being executed on a memory cell corresponding to the second conductive layer or the third conductive layer.

公开(公告)号：US11594285B2

公开(公告)日：2023-02-28

申请号：US17481892

申请日：2021-09-22

Applicant: Kioxia Corporation

Inventor： Takeshi Hioka ,  Tsukasa Kobayashi ,  Koji Kato ,  Yuki Shimizu ,  Hiroshi Maejima

IPC: G11C16/26 ,  G11C16/24 ,  G11C16/08 ,  H01L27/11568 ,  G11C16/10 ,  H01L27/11582 ,  G11C16/30

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells; a first word line connected to the first and second memory cells; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first sense amplifier connected to the first bit line; a second sense amplifier connected to the second bit line; a voltage generation circuit; and a first row decoder which supplies a voltage to the first word line.

公开(公告)号：US11908511B2

公开(公告)日：2024-02-20

申请号：US17645814

申请日：2021-12-23

Applicant: KIOXIA CORPORATION

Inventor： Koji Kato

IPC: G11C16/08 ,  G11C11/4096 ,  G11C11/4074 ,  G11C5/06 ,  G11C11/4076 ,  G11C11/408

CPC classification number: G11C11/4096 ,  G11C5/063 ,  G11C11/408 ,  G11C11/4074 ,  G11C11/4076

Abstract: A semiconductor memory device includes a memory string, first wirings electrically connected to the memory string, second wirings electrically connected to the first wirings, transistors electrically connected between the first wirings and the second wirings, and a third wiring connected to gate electrodes of the transistors in common. The memory string includes memory transistors connected in series. Gate electrodes of the memory transistors are connected to the first wirings. The semiconductor memory device executes a first read operation in response to an input of a first command set, and executes a second read operation in response to an input of a second command set. A first voltage that turns the transistors ON is applied to the third wiring from an end of the first read operation to a start of the second read operation.

公开(公告)号：US11862248B2

公开(公告)日：2024-01-02

申请号：US18161274

申请日：2023-01-30

Applicant: Kioxia Corporation

Inventor： Mai Shimizu ,  Koji Kato ,  Yoshihiko Kamata ,  Mario Sako

IPC: G11C16/08 ,  G11C16/30 ,  G11C16/26 ,  G11C16/04 ,  G11C11/56 ,  G11C16/24 ,  G11C16/32 ,  G11C16/34

CPC classification number: G11C16/08 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3427

Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.

公开(公告)号：US20220157380A1

公开(公告)日：2022-05-19

申请号：US17591216

申请日：2022-02-02

Applicant: KIOXIA CORPORATION

Inventor： Mai Shimizu ,  Koji Kato ,  Yoshihiko Kamata ,  Mario Sako

IPC: G11C16/08 ,  G11C16/30 ,  G11C16/26 ,  G11C16/04 ,  G11C11/56 ,  G11C16/24 ,  G11C16/32 ,  G11C16/34

Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.

公开(公告)号：US11205482B2

公开(公告)日：2021-12-21

申请号：US16806282

申请日：2020-03-02

Applicant: KIOXIA CORPORATION

Inventor： Takeshi Hioka ,  Koji Kato

IPC: G11C16/08 ,  G11C16/12 ,  G11C16/26 ,  G11C7/22 ,  G11C16/34 ,  G11C16/04 ,  G11C16/24

Abstract: A semiconductor storage device includes a plurality of memory cells connected to each other in series, a plurality of word lines respectively connected to gates of the plurality of memory cells, and a control circuit configured to perform a read operation by applying a first voltage higher than ground voltage to the plurality of word lines during a first time period at the beginning of which each word line is at ground voltage, applying a second voltage lower than the first voltage to a first word line during a second time period subsequent to the first time period, applying a third voltage higher than the second voltage to the first word line during a third time period subsequent to the second time period, and determining data of the memory cells connected to the first word line while all portions of the first word line are at the third voltage.

公开(公告)号：US11133066B2

公开(公告)日：2021-09-28

申请号：US16934978

申请日：2020-07-21

Applicant: KIOXIA CORPORATION

Inventor： Yuki Shimizu ,  Yoshihiko Kamata ,  Tsukasa Kobayashi ,  Hideyuki Kataoka ,  Koji Kato ,  Takumi Fujimoto ,  Yoshinao Suzuki ,  Yuui Shimizu

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C7/24 ,  G11C16/30 ,  G11C16/10 ,  G11C7/10 ,  G11C16/28

Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.