公开(公告)号：US20240365549A1

公开(公告)日：2024-10-31

申请号：US18766417

申请日：2024-07-08

Applicant: KIOXIA CORPORATION

Inventor： Yoshiaki FUKUZUMI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Masaru KITO ,  Hiroyasu TANAKA ,  Yosuke KOMORI ,  Megumi ISHIDUKI ,  Hideaki AOCHI

IPC: H10B43/27 ,  G11C16/04 ,  H01L29/51 ,  H10B41/20 ,  H10B41/27 ,  H10B43/20 ,  H10B43/40 ,  H10B43/50 ,  H10B99/00

CPC classification number: H10B43/27 ,  G11C16/0483 ,  H01L29/513 ,  H10B41/27 ,  H10B43/20 ,  H10B43/40 ,  H10B43/50 ,  H10B99/00 ,  H10B41/20

Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.

公开(公告)号：US20240365540A1

公开(公告)日：2024-10-31

申请号：US18771585

申请日：2024-07-12

Applicant: Kioxia Corporation

Inventor： Yoshihiro AKUTSU ,  Ryota KATSUMATA

IPC: H10B41/27 ,  H01L21/74 ,  H01L21/768 ,  H01L23/535 ,  H01L25/00 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B41/27 ,  H01L21/743 ,  H01L21/76889 ,  H01L23/535 ,  H01L25/00 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H01L2924/0002

Abstract: This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.

公开(公告)号：US20240138150A1

公开(公告)日：2024-04-25

申请号：US18398863

申请日：2023-12-28

Applicant: Kioxia Corporation

Inventor： Masaru KITO ,  Hideaki AOCHI ,  Ryota KATSUMATA ,  Akihiro NITAYAMA ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Yoshiaki FUKUZUMI ,  Yasuyuki MATSUOKA ,  Mitsuru SATO

IPC: H10B43/27 ,  H01L21/822 ,  H01L27/06 ,  H01L27/105 ,  H10B41/27 ,  H10B43/20 ,  H10B43/40 ,  H10B69/00

CPC classification number: H10B43/27 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H10B41/27 ,  H10B43/20 ,  H10B43/40 ,  H10B69/00 ,  G11C16/0483

Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

公开(公告)号：US20240008276A1

公开(公告)日：2024-01-04

申请号：US18465223

申请日：2023-09-12

Applicant: KIOXIA CORPORATION

Inventor： Yoshiaki FUKUZUMI ,  Ryota KATSUMATA ,  Masaru KITO ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Yosuke KOMORI ,  Megumi ISHIDUKI ,  Junya MATSUNAMI ,  Tomoko FUJIWARA ,  Hideaki AOCHI ,  Ryouhei KIRISAWA ,  Yoshimasa MIKAJIRI ,  Shigeto OOTA

IPC: H10B43/27 ,  H01L29/66 ,  H01L29/792 ,  H10B43/20 ,  H01L21/223 ,  H01L21/265 ,  H01L29/78 ,  H01L29/04 ,  H01L29/16 ,  H01L29/423 ,  H01L29/49 ,  H01L29/10

CPC classification number: H10B43/27 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926 ,  H10B43/20 ,  H01L21/223 ,  H01L21/265 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/04 ,  H01L29/16 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/1037

Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

公开(公告)号：US20220293621A1

公开(公告)日：2022-09-15

申请号：US17409741

申请日：2021-08-23

Applicant: KIOXIA CORPORATION

Inventor： Yusuke OCHI ,  Ryota KATSUMATA ,  Masahiro FUKUDA

IPC: H01L27/11565 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor storage device includes a plurality of conductor layers that are stacked in a first direction and a plurality of bit lines that are spaced from each other in a second direction. Pillars extend in the first direction through the conductor layers and are electrically connected to the bit lines. An insulator is provided that divides the region in which the plurality of pillars are disposed into adjacent regions. An interval between the pillars in an end row adjacent to the insulator is greater than an interval between the pillars in an inner row that is not directly adjacent to the insulator.

公开(公告)号：US20240251561A1

公开(公告)日：2024-07-25

申请号：US18440623

申请日：2024-02-13

Applicant: Kioxia Corporation

Inventor： Tomoo HISHIDA ,  Sadatoshi MURAKAMI ,  Ryota KATSUMATA ,  Masao IWASE

IPC: H10B43/35 ,  H01L21/8234 ,  H10B43/27 ,  H10B43/50

CPC classification number: H10B43/35 ,  H01L21/823437 ,  H10B43/27 ,  H10B43/50

Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.

公开(公告)号：US20230146470A1

公开(公告)日：2023-05-11

申请号：US18091728

申请日：2022-12-30

Applicant: KIOXIA CORPORATION

Inventor： Yoshiaki FUKUZUMI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Masaru KITO ,  Hiroyasu TANAKA ,  Yosuke KOMORI ,  Megumi ISHIDUKI ,  Hideaki AOCHI

IPC: H10B43/27 ,  G11C16/04 ,  H10B41/27 ,  H10B43/40 ,  H10B43/50 ,  H10B43/20 ,  H01L27/105 ,  H01L29/51

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/1052 ,  H01L29/513 ,  H01L27/11551

Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritahle memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of colunmar portions a charge storage layer formed to surround the side surfaces of the columnar portions: and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.

公开(公告)号：US20230088310A1

公开(公告)日：2023-03-23

申请号：US17991694

申请日：2022-11-21

Applicant: KIOXIA CORPORATION

Inventor： Tomoo HISHIDA ,  Sadatoshi MURAKAMI ,  Ryota KATSUMATA ,  Masao IWASE

IPC: H01L27/1157 ,  H01L21/8234 ,  H01L27/11575 ,  H01L27/11582

Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.

公开(公告)号：US20220139955A1

公开(公告)日：2022-05-05

申请号：US17576164

申请日：2022-01-14

Applicant: Kioxia Corporation

Inventor： Yoshiaki FUKUZUMI ,  Ryota KATSUMATA ,  Masaru KITO ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Yosuke KOMORI ,  Megumi ISHIDUKI ,  Junya MATSUNAMI ,  Tomoko FUJIWARA ,  Hideaki AOCHI ,  Ryouhei KIRISAWA ,  Yoshimasa MIKAJIRI ,  Shigeto OOTA

IPC: H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11578 ,  H01L21/223 ,  H01L21/265 ,  H01L29/78 ,  H01L29/04 ,  H01L29/16 ,  H01L29/423 ,  H01L29/49 ,  H01L29/10

Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

公开(公告)号：US20210126012A1

公开(公告)日：2021-04-29

申请号：US17141534

申请日：2021-01-05

Applicant: Kioxia Corporation

Inventor： Masaru KITO ,  Hideaki AOCHI ,  Ryota KATSUMATA ,  Akihiro NITAYAMA ,  Masaru KIDOH ,  Hiroyasu TANAKA ,  Yoshiaki FUKUZUMI ,  Yasuyuki MATSUOKA ,  Mitsuru SATO

IPC: H01L27/11582 ,  H01L21/822 ,  H01L27/06 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11556

Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.