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    Semiconductor memory with ferroelectric capacitors
    12.
    发明授权
    Semiconductor memory with ferroelectric capacitors 失效
    半导体存储器与铁电电容器

    公开(公告)号：US5615145A

    公开(公告)日：1997-03-25

    申请号：US580090

    申请日：1995-12-20

    Applicant: Kan Takeuchi ,  Katsumi Matsuno ,  Kazuhiko Kajiyama ,  Osamu Nagashima ,  Masatoshi Hasegawa

    Inventor： Kan Takeuchi ,  Katsumi Matsuno ,  Kazuhiko Kajiyama ,  Osamu Nagashima ,  Masatoshi Hasegawa

    IPC: G11C11/22 ,  G11C14/00 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108

    CPC classification number: G11C11/22

    Abstract: A semiconductor memory which includes a plurality of memory cells each having first and second capacitors connected in series and a field-effect transistor whose source or drain is connected to a node between the first and second capacitors. The memory cells are arranged at intersections of bit lines and word lines thereby forming a matrix. The first capacitor of each memory cell is a ferroelectric capacitor using a ferroelectric material as an insulating film. A plate electrode of the first capacitor of each memory cell is held at a first potential when the memory is operated in a first mode and the plate electrode of the first capacitor is held at a second potential when the memory is operated in a second mode. The first potential is different from the second potential.

    Abstract translation: 一种半导体存储器，包括多个存储单元，每个存储单元均具有串联连接的第一和第二电容器，以及源极或漏极连接到第一和第二电容器之间的节点的场效应晶体管。 存储单元布置在位线和字线的交点处，从而形成矩阵。 每个存储单元的第一电容器是使用铁电材料作为绝缘膜的铁电电容器。 当存储器以第一模式操作时，每个存储单元的第一电容器的平板电极被保持在第一电位，并且当存储器在第二模式下操作时，第一电容器的平板电极被保持在第二电位。 第一个潜力与第二个潜力不同。

    Ferroelectric memory
    13.
    发明授权
    Ferroelectric memory 失效
    铁电存储器

    公开(公告)号：US5455786A

    公开(公告)日：1995-10-03

    申请号：US257542

    申请日：1994-06-09

    Applicant: Kan Takeuchi ,  Katsumi Matsuno ,  Yoshinobu Nakagome ,  Masakazu Aoki

    Inventor： Kan Takeuchi ,  Katsumi Matsuno ,  Yoshinobu Nakagome ,  Masakazu Aoki

    IPC: H01L27/10 ,  G11C11/22 ,  G11C14/00 ,  H01L21/8246 ,  H01L27/105

    CPC classification number: G11C11/22

    Abstract: A highly reliable and high speed ferroelectric memory having high degree of integration is provided. In a ferroelectric memory having a plurality of memory cells M1 each constituted by one transistor and one ferroelectric capacitor. In the normal operation, the ferroelectric memory is used as a volatile memory in which a voltage of a storage node ST1 is utilized as the stored information. Both an electric potential at a plate PL1 of the ferroelectric capacitor and a precharge electric potential on a data line DL1(j) are made Vcc/2.

    Abstract translation: 提供了具有高集成度的高可靠性和高速铁电存储器。 在具有由一个晶体管和一个铁电电容器构成的多个存储单元M1的铁电存储器中。 在正常操作中，铁电存储器用作其中使用存储节点ST1的电压作为存储信息的易失性存储器。 铁电电容器的板PL1上的电位和数据线DL1（j）上的预充电电位都为Vcc / 2。

    Semiconductor device, microcomputer and flash memory
    18.
    发明授权
    Semiconductor device, microcomputer and flash memory 有权
    半导体器件，微机和闪存

    公开(公告)号：US06477090B2

    公开(公告)日：2002-11-05

    申请号：US09939708

    申请日：2001-08-28

    Applicant: Takashi Yamaki ,  Kan Takeuchi ,  Mitsuru Hiraki ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Masamichi Fujito

    Inventor： Takashi Yamaki ,  Kan Takeuchi ,  Mitsuru Hiraki ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Masamichi Fujito

    IPC: G11C700

    CPC classification number: G11C29/50008 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/28 ,  G11C16/30 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

    Abstract: A semiconductor device whose characteristics are highly reliably regulated for circuits whose desired characteristics need to be realized without being affect by unevenness in device characteristics is to be provided. A replica MOS transistor for amperage measurement connected to an external measuring terminal is provided. A delay circuit and other circuits whose desired characteristics are to be realized have a constant current source MOS transistor formed in the same process as the replica MOS transistor, and a trimming voltage vtri is commonly applied to the respective gates of the constant current source MOS transistor and the replica MOS transistor. Trimming data determined on the basis of an amperage measured from the external measuring terminal are stored into a memory means such as an electrically rewritable non-volatile memory or the like. The trimming data determine the trimming voltage vtri.

    Abstract translation: 提供一种其特性对于其所需特性需要实现而不受设备特性不均匀影响的电路高度可靠地调节的半导体器件。 提供连接到外部测量端子的用于安培数测量的复制MOS晶体管。 要实现其期望特性的延迟电路和其它电路具有与复制MOS晶体管相同的工艺形成的恒流源MOS晶体管，并且微调电压vtri通常施加到恒流源MOS晶体管的各个栅极 和复制MOS晶体管。 基于从外部测量终端测量的电流强度确定的修整数据被存储到诸如电可重写非易失性存储器等的存储装置中。 修整数据确定修整电压vtri。

    Semiconductor memory device
    20.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5726930A

    公开(公告)日：1998-03-10

    申请号：US653236

    申请日：1996-05-24

    Applicant: Masatoshi Hasegawa ,  Kazuhiko Kajigaya ,  Kan Takeuchi ,  Katsumi Matsuno ,  Osamu Nagashima

    Inventor： Masatoshi Hasegawa ,  Kazuhiko Kajigaya ,  Kan Takeuchi ,  Katsumi Matsuno ,  Osamu Nagashima

    IPC: G11C14/00 ,  G11C11/22 ,  G11C11/401 ,  G11C11/404 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

    CPC classification number: G11C11/22 ,  G11C11/404

    Abstract: A semiconductor memory device capable of simultaneously providing volatile and non-volatile portions is disclosed having a plurality of memory mats, and a plurality of plate electrodes and a plurality of memory mats each provided in one-to-one correspondence with the memory maps. The memory mats each include a plurality of word lines, a plurality of bit lines and a plurality of memory cells provided at the intersections of the word lines and the bit lines. The memory cells each include an information storage capacitor having a ferroelectric film, and an address selection MOSFET. The information storage capacitor has a pair of electrodes, one of which is connected to the plate electrode that corresponds to the memory mat in which the information storage capacitor is included. A first voltage or a second voltage is selectively applied to each of the plate electrodes according to data held in the memory circuit corresponding to the plate electrode. When the first voltage is applied to the plate electrode, the information storage capacitors connected to the plate electrode are made incapable of polarization reversal irrespective of a binary write signal given to the bit lines. When the second voltage is applied to the plate electrode, the information storage capacitors connected to the plate electrode are made capable of polarization inversion in response to a binary write signal given to the bit lines.

    Abstract translation: 公开了能够同时提供易失性和非易失性部分的半导体存储器件，其具有多个存储器垫，以及多个板电极和多个存储器垫，每个存储垫与存储器映射图一一对应地提供。 存储器垫每个都包括多个字线，多个位线和设置在字线和位线的交点处的多个存储单元。 存储单元各自包括具有铁电膜的信息存储电容器和地址选择MOSFET。 信息存储电容器具有一对电极，其中一个电极连接到对应于包括信息存储电容器的存储器垫的平板电极。 根据与平板电极相对应的存储电路中保存的数据，选择性地向每个平板电极施加第一电压或第二电压。 当第一电压施加到平板电极时，连接到平板电极的信息存储电容器不会产生极化反转，而与给定位线的二进制写入信号无关。 当第二电压施加到平板电极时，连接到平板电极的信息存储电容器响应于给定位线的二进制写入信号而能够进行极化反转。

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