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    Resistive Memory Structure with Buffer Layer
    13.
    发明申请
    Resistive Memory Structure with Buffer Layer 有权
    具有缓冲层的电阻式存储器结构

    公开(公告)号：US20100276658A1

    公开(公告)日：2010-11-04

    申请号：US12836304

    申请日：2010-07-14

    申请人： Wei-Chih Chien ,  Kuo-Pin Chang ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    发明人： Wei-Chih Chien ,  Kuo-Pin Chang ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    IPC分类号： H01L45/00

    CPC分类号： H01L45/04 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1633 ,  Y10S438/90

    摘要： A memory device comprises first and second electrodes with a memory element and a buffer layer located between and electrically coupled to them. The memory element comprises one or more metal oxygen compounds. The buffer layer comprises at least one of an oxide and a nitride. Another memory device comprises first and second electrodes with a memory element and a buffer layer, having a thickness of less than 50 Å, located between and electrically coupled to them. The memory comprises one or more metal oxygen compounds. An example of a method of fabricating a memory device includes forming first and second electrodes. A memory, located between and electrically coupled to the first and the second electrodes, is formed; the memory comprises one or more metal oxygen compounds and the buffer layer comprises at least one of an oxide and a nitride.

    摘要翻译： 存储器件包括具有存储元件的第一和第二电极以及位于它们之间并与之电耦合的缓冲层。 记忆元件包括一种或多种金属氧化合物。 缓冲层包括氧化物和氮化物中的至少一种。 另一个存储器件包括具有存储元件和缓冲层的第一和第二电极，其厚度小于50，位于它们之间并与之电耦合。 记忆体包括一种或多种金属氧化合物。 制造存储器件的方法的一个例子包括形成第一和第二电极。 形成位于第一和第二电极之间并电耦合到第一和第二电极的存储器; 存储器包括一种或多种金属氧化合物，并且缓冲层包括氧化物和氮化物中的至少一种。

    Resistor random access memory structure having a defined small area of electrical contact
    15.
    发明授权
    Resistor random access memory structure having a defined small area of electrical contact 有权
    电阻随机存取存储器结构具有限定的小的电接触面积

    公开(公告)号：US09018615B2

    公开(公告)日：2015-04-28

    申请号：US11833563

    申请日：2007-08-03

    申请人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

    发明人： Erh-Kun Lai ,  ChiaHua Ho ,  Kuang Yeu Hsieh

    IPC分类号： H01L47/00 ,  H01L45/00

    CPC分类号： H01L45/16 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144

    摘要： A memory cell device, of the type that includes a memory material switchable between electrical property states by application of energy, includes first and second electrodes, a plug of memory material (such as phase change material) which is in electrical contact with the second electrode, and an electrically conductive film which is supported by a dielectric form and which is in electrical contact with the first electrode and with the memory material plug. The dielectric form is wider near the first electrode, and is narrower near the phase change plug. The area of contact of the conductive film with the phase change plug is defined in part by the geometry of the dielectric form over which the conductive film is formed. Also, methods for making the device include steps of constructing a dielectric form over a first electrode, and forming a conductive film over the dielectric form.

    摘要翻译： 包括能够通过施加能量在电性能状态之间切换的存储材料的存储单元装置包括第一和第二电极，与第二电极电接触的存储材料（例如相变材料）插头 以及由电介质形式支撑并与第一电极和记忆材料塞电接触的导电膜。 电介质形式在第一电极附近较宽，在相变插头附近较窄。 导电膜与相变插塞的接触面积部分地由形成导电膜的电介质形状的几何形状限定。 此外，制造该器件的方法包括在第一电极上构建电介质形式，以及在电介质形式上形成导电膜的步骤。

    Resistance random access memory structure for enhanced retention
    16.
    发明授权
    Resistance random access memory structure for enhanced retention 有权
    电阻随机存取存储器结构，增强保留

    公开(公告)号：US08587983B2

    公开(公告)日：2013-11-19

    申请号：US13281266

    申请日：2011-10-25

    申请人： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    发明人： ChiaHua Ho ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

    IPC分类号： H01L45/00

    CPC分类号： H01L45/1608 ,  H01L45/04 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1625

    摘要： A bistable resistance random access memory is described for enhancing the data retention in a resistance random access memory member. A dielectric member, e.g. the bottom dielectric member, underlies the resistance random access memory member which improves the SET/RESET window in the retention of information. The deposition of the bottom dielectric member is carried out by a plasma-enhanced chemical vapor deposition or by high-density-plasma chemical vapor deposition. One suitable material for constructing the bottom dielectric member is a silicon oxide. The bistable resistance random access memory includes a bottom dielectric member disposed between a resistance random access member and a bottom electrode or bottom contact plug. Additional layers including a bit line, a top contact plug, and a top electrode disposed over the top surface of the resistance random access memory member. Sides of the top electrode and the resistance random access memory member are substantially aligned with each other.

    摘要翻译： 描述了双稳态电阻随机存取存储器，用于增强电阻随机存取存储器件中的数据保持。 电介质构件，例如 底部电介质构件位于电阻随机存取存储器构件的下方，其改善了保留信息中的SET / RESET窗口。 底部电介质构件的沉积通过等离子体增强化学气相沉积或通过高密度 - 等离子体化学气相沉积来进行。 用于构造底部电介质构件的一种合适的材料是氧化硅。 双稳态随机存取存储器包括设置在电阻随机存取构件和底部电极或底部接触插塞之间的底部电介质构件。 附加层包括位线，顶部接触插塞和设置在电阻随机存取存储器构件顶表面上的顶部电极。 顶部电极和电阻随机存取存储器构件的侧面基本上彼此对准。

    Silicon on insulator and thin film transistor bandgap engineered split gate memory
    17.
    发明授权
    Silicon on insulator and thin film transistor bandgap engineered split gate memory 有权
    硅绝缘体和薄膜晶体管带隙设计的分离栅极存储器

    公开(公告)号：US08482052B2

    公开(公告)日：2013-07-09

    申请号：US12056489

    申请日：2008-03-27

    申请人： Hang-Ting Lue ,  Erh-Kun Lai

    发明人： Hang-Ting Lue ,  Erh-Kun Lai

    IPC分类号： H01L29/792 ,  H01L29/788

    CPC分类号： H01L29/66833 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/0491 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11551 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/792

    摘要： Thin film transistor memory cells are stackable, and employ bandgap engineered tunneling layers in a junction free, NAND configuration, that can be arranged in 3D arrays. The memory cells have a channel region in a semiconductor strip formed on an insulating layer, a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure having a multilayer structure including at least one layer having a hole-tunneling barrier height lower than that at the interface with the channel region, a charge storage layer disposed above the tunnel dielectric structure, an insulating layer disposed above the charge storage layer, and a gate electrode disposed above the insulating layer.

    摘要翻译： 薄膜晶体管存储单元是可堆叠的，并且采用无结构的NAND配置的带隙工程隧道层，其可以排列成3D阵列。 所述存储单元具有在绝缘层上形成的半导体条中的沟道区，设置在所述沟道区上方的隧道电介质结构，所述隧道电介质结构具有多层结构，所述多层结构包括至少一层具有低于空穴穿透势垒高度的层。 在与沟道区域的界面处，设置在隧道介电结构上方的电荷存储层，设置在电荷存储层上方的绝缘层和设置在绝缘层上方的栅电极。

    METHOD OF FORMING MEMORY CELL ACCESS DEVICE
    18.
    发明申请
    METHOD OF FORMING MEMORY CELL ACCESS DEVICE 有权
    形成记忆细胞存取装置的方法

    公开(公告)号：US20120326265A1

    公开(公告)日：2012-12-27

    申请号：US13168753

    申请日：2011-06-24

    申请人： Erh-Kun Lai ,  Hsiang-Lan Lung ,  Edward Kiewra

    发明人： Erh-Kun Lai ,  Hsiang-Lan Lung ,  Edward Kiewra

    IPC分类号： H01L21/762 ,  H01L27/08 ,  B82Y99/00

    CPC分类号： H01L27/1021 ,  H01L27/101

    摘要： A memory device includes an access device including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor region having a second conductivity type opposite the first conductivity type. Both the first and the second doped semiconductor regions are formed in a single-crystalline semiconductor body, and define a p-n junction between them. The first and second doped semiconductor regions are implemented in isolated parallel ridges formed in the single-crystal semiconductor body. Each ridge is crenellated, and the crenellations define semiconductor islands; the first doped semiconductor region occupies a lower portion of the islands and an upper part of the ridge, and the second doped semiconductor region occupies an upper portion of the islands, so that the p-n junctions are defined within the islands.

    摘要翻译： 存储器件包括一个存取器件，它包括具有第一导电类型的第一掺杂半导体区域和具有与第一导电类型相反的第二导电类型的第二掺杂半导体区域。 第一掺杂半导体区域和第二掺杂半导体区域均形成在单晶半导体本体中，并且在它们之间限定p-n结。 第一和第二掺杂半导体区域被实现在形成在单晶半导体本体中的隔离的平行脊中。 每个山脊都是锯齿状的，扇形界定半岛; 第一掺杂半导体区域占据岛的下部和脊的上部，并且第二掺杂半导体区占据岛的上部，从而在岛内限定p-n结。

    INJECTION METHOD WITH SCHOTTKY SOURCE/DRAIN
    20.
    发明申请
    INJECTION METHOD WITH SCHOTTKY SOURCE/DRAIN 审中-公开
    注射方法与肖特源/排水

    公开(公告)号：US20120220111A1

    公开(公告)日：2012-08-30

    申请号：US13463264

    申请日：2012-05-03

    申请人： Yi-Hsuan Hsiao ,  Erh-Kun Lai ,  Hang-Ting Lue

    发明人： Yi-Hsuan Hsiao ,  Erh-Kun Lai ,  Hang-Ting Lue

    IPC分类号： H01L21/04

    CPC分类号： H01L29/665 ,  G11C16/0408 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

    摘要： An injection method for non-volatile memory cells with a Schottky source and drain is described. Carrier injection efficiency is controlled by an interface characteristic of silicide and silicon. A Schottky barrier is modified by controlling an overlap of a gate and a source/drain and by controlling implantation, activation and/or gate processes.

    摘要翻译： 描述了具有肖特基源和漏极的非易失性存储单元的注入方法。 载流子注入效率由硅化物和硅的界面特性控制。 通过控制栅极和源极/漏极的重叠以及通过控制注入，激活和/或栅极过程来修改肖特基势垒。