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21 条记录 (耗时 0.031 秒)

    Semiconductor devices and methods of fabricating the same
    14.
    发明授权
    Semiconductor devices and methods of fabricating the same 有权
    半导体器件及其制造方法

    公开(公告)号：US08587052B2

    公开(公告)日：2013-11-19

    申请号：US13402171

    申请日：2012-02-22

    申请人： Jang-Gn Yun ,  Kwang-Soo Seol ,  Jungdal Choi

    发明人： Jang-Gn Yun ,  Kwang-Soo Seol ,  Jungdal Choi

    IPC分类号： H01L29/792

    CPC分类号： H01L29/7926 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66833

    摘要： One example embodiment of a semiconductor device includes a memory cell array formed on a substrate. The memory cell array includes a gate stack including alternating conductive and insulating layers. A first lower conductive layer in the gate stack has a portion disposed below a first upper conductive layer in the gate stack, and a first contact area of the first lower conductive layer is disposed higher than a second contact area of the first upper conductive layer. The semiconductor device further includes first and second contact plugs extending into the gate stack to contact the first and second contact areas, respectively.

    摘要翻译： 半导体器件的一个示例实施例包括形成在衬底上的存储单元阵列。 存储单元阵列包括包括交替的导电和绝缘层的栅极堆叠。 栅堆叠中的第一下导电层具有设置在栅极堆叠中的第一上导电层下方的部分，并且第一下导电层的第一接触区域设置为高于第一上导电层的第二接触面积。 半导体器件还包括分别延伸到栅极堆叠中以分别接触第一和第二接触区域的第一和第二接触插塞。

    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME
    15.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20130032875A1

    公开(公告)日：2013-02-07

    申请号：US13402171

    申请日：2012-02-22

    申请人： Jang-Gn Yun ,  Kwang-Soo Seol ,  Jungdal Choi

    发明人： Jang-Gn Yun ,  Kwang-Soo Seol ,  Jungdal Choi

    IPC分类号： H01L29/792 ,  H01L29/78

    CPC分类号： H01L29/7926 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66833

    摘要： One example embodiment of a semiconductor device includes a memory cell array formed on a substrate. The memory cell array includes a gate stack including alternating conductive and insulating layers. A first lower conductive layer in the gate stack has a portion disposed below a first upper conductive layer in the gate stack, and a first contact area of the first lower conductive layer is disposed higher than a second contact area of the first upper conductive layer. The semiconductor device further includes first and second contact plugs extending into the gate stack to contact the first and second contact areas, respectively.

    摘要翻译： 半导体器件的一个示例实施例包括形成在衬底上的存储单元阵列。 存储单元阵列包括包括交替的导电和绝缘层的栅极堆叠。 栅堆叠中的第一下导电层具有设置在栅极堆叠中的第一上导电层下方的部分，并且第一下导电层的第一接触区域设置为高于第一上导电层的第二接触面积。 半导体器件还包括分别延伸到栅极堆叠中以分别接触第一和第二接触区域的第一和第二接触插塞。

    METHODS OF MANUFACTURING VERTICAL SEMICONDUCTOR DEVICES
    16.
    发明申请
    METHODS OF MANUFACTURING VERTICAL SEMICONDUCTOR DEVICES 有权
    制造垂直半导体器件的方法

    公开(公告)号：US20120058629A1

    公开(公告)日：2012-03-08

    申请号：US13212485

    申请日：2011-08-18

    申请人： Byung-Kwan You ,  Kwang-Soo Seol ,  Young-Woo Park ,  Jin-Soo Lim

    发明人： Byung-Kwan You ,  Kwang-Soo Seol ,  Young-Woo Park ,  Jin-Soo Lim

    IPC分类号： H01L21/28 ,  H01L21/20

    CPC分类号： H01L21/28282 ,  H01L21/02104 ,  H01L27/11582 ,  H01L29/7926

    摘要： Methods of manufacturing vertical semiconductor devices may include forming a mold structure including sacrificial layers and insulating interlayers with a first opening formed therethrough. The sacrificial layers and the insulating interlayers may be stacked repeatedly and alternately on a substrate. The first opening may expose the substrate. Blocking layers may be formed by oxidizing portions of the sacrificial layers exposed by the first opening. A first semiconductor layer pattern, a charge trapping layer pattern and a tunnel insulation layer pattern, respectively, may be formed on the sidewall of the first opening. A second semiconductor layer may be formed on the first polysilicon layer pattern and the bottom of the first opening. The sacrificial layers and the insulating interlayers may be partially removed to form a second opening. The sacrificial layers may be removed to form grooves between the insulating interlayers. Control gate electrodes may be formed in the grooves.

    摘要翻译： 制造垂直半导体器件的方法可以包括形成包括牺牲层和绝缘夹层的模具结构，其中形成有第一开口。 牺牲层和绝缘夹层可以重复地和交替地层叠在基板上。 第一开口可能暴露基板。 可以通过氧化由第一开口暴露的牺牲层的部分来形成阻挡层。 分别可以在第一开口的侧壁上形成第一半导体层图案，电荷俘获层图案和隧道绝缘层图案。 可以在第一多晶硅层图案和第一开口的底部上形成第二半导体层。 可以部分去除牺牲层和绝缘夹层以形成第二开口。 可以去除牺牲层以在绝缘夹层之间形成凹槽。 控制栅电极可以形成在凹槽中。

    Gate structure, semiconductor memory device having the gate structure and methods of fabricating the same
    18.
    发明申请
    Gate structure, semiconductor memory device having the gate structure and methods of fabricating the same 审中-公开
    门结构，具有栅极结构的半导体存储器件及其制造方法

    公开(公告)号：US20100109074A1

    公开(公告)日：2010-05-06

    申请号：US12654029

    申请日：2009-12-08

    申请人： Kwang-Soo Seol ,  Byung-Kl Kim ,  Eun-Kyung Lee ,  Yo-Sep Min ,  Kyung-Sang Cho ,  Jae-Ho Lee ,  Jae-Young Choi

    发明人： Kwang-Soo Seol ,  Byung-Kl Kim ,  Eun-Kyung Lee ,  Yo-Sep Min ,  Kyung-Sang Cho ,  Jae-Ho Lee ,  Jae-Young Choi

    IPC分类号： H01L29/792

    CPC分类号： H01L29/42332 ,  B82Y10/00 ,  H01L29/40114 ,  H01L29/42348

    摘要： A gate structure using nanodots as a trap site, a semiconductor device having the gate structure and methods of fabricating the same are provided. The gate structure may include a tunneling layer, a plurality of nanodots on the tunneling layer, and a control insulating layer including a high-k dielectric layer on the tunneling layer and the nanodots. A semiconductor memory device may further include a semiconductor substrate, the gate structure according to example embodiments on the semiconductor substrate and a first impurity region and a second impurity region in the semiconductor substrate, wherein the gate structure is in contact with the first and second impurity regions.

    摘要翻译： 提供了使用纳米点作为陷阱位置的栅极结构，具有栅极结构的半导体器件及其制造方法。 栅极结构可以包括隧道层，隧道层上的多个纳米点，以及在隧道层和纳米点上包括高k电介质层的控制绝缘层。 半导体存储器件还可以包括半导体衬底，半导体衬底上的示例性实施例的栅极结构和半导体衬底中的第一杂质区和第二杂质区，其中栅极结构与第一和第二杂质接触 地区。

    Gate structure including multi-tunneling layer and method of fabricating the same, non-volatile memory device and method of fabricating the same
    20.
    发明申请
    Gate structure including multi-tunneling layer and method of fabricating the same, non-volatile memory device and method of fabricating the same 审中-公开
    包括多隧道层的栅结构及其制造方法，非易失性存储器件及其制造方法

    公开(公告)号：US20070114572A1

    公开(公告)日：2007-05-24

    申请号：US11600737

    申请日：2006-11-17

    申请人： Kwang-Soo Seol ,  Woong-Chul Shin ,  Byung Kim ,  Eun-Kyung Lee ,  Kyung-Sang Cho

    发明人： Kwang-Soo Seol ,  Woong-Chul Shin ,  Byung Kim ,  Eun-Kyung Lee ,  Kyung-Sang Cho

    IPC分类号： H01L29/76

    CPC分类号： H01L29/42332 ,  B82Y10/00 ,  H01L27/115 ,  H01L29/7881

    摘要： Provided is a gate structure including a multi-tunneling layer and method of fabricating the same. Also provided is a nanodot semiconductor memory device including such gate structure and method of fabricating the same. The gate structure may include a first insulation layer, a second insulation layer, a charge storage layer including nanodots and formed on the second insulation layer, a third insulation layer formed on the charge storage layer, and a gate electrode layer formed on the third insulation layer. There may also be a nanodot semiconductor memory device including a semiconductor substrate, in which a first impurity region and a second impurity region may be formed, and including the gate structure formed on the semiconductor substrate which contacts the first and second impurity regions. The second insulation layer may be formed on the first insulation layer and may include a material whose energy level may be lower than an energy level of the conduction band of the first insulation layer and higher an energy level of the valence band of the first insulation layer.

    摘要翻译： 提供一种包括多隧道层的栅极结构及其制造方法。 还提供了包括这种栅极结构的纳米点半导体存储器件及其制造方法。 栅极结构可以包括第一绝缘层，第二绝缘层，包括纳米点并形成在第二绝缘层上的电荷存储层，形成在电荷存储层上的第三绝缘层，以及形成在第三绝缘层上的栅电极层 层。 还可以存在包括可以形成第一杂质区域和第二杂质区域的半导体衬底的纳米点半导体存储器件，并且包括形成在与第一和第二杂质区域接触的半导体衬底上的栅极结构。 第二绝缘层可以形成在第一绝缘层上，并且可以包括其能级可以低于第一绝缘层的导带的能级的材料，并且第一绝缘层的价带的能级越高 。