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27 条记录 (耗时 0.017 秒)

    Memory cell configuration and fabrication method
    11.
    发明授权
    Memory cell configuration and fabrication method 有权
    存储单元配置和制造方法

    公开(公告)号：US06417043B1

    公开(公告)日：2002-07-09

    申请号：US09528268

    申请日：2000-03-17

    申请人： Lothar Risch ,  Wolfgang Rösner ,  Ties Ramcke ,  Hermann Jacobs

    发明人： Lothar Risch ,  Wolfgang Rösner ,  Ties Ramcke ,  Hermann Jacobs

    IPC分类号： H01L2976

    CPC分类号： H01L21/822 ,  G11C17/10 ,  H01L27/101

    摘要： Resistors are connected between word lines and bit lines running transversely with respect thereto. The resistors have a higher resistance than the word lines and the bit lines. The bit lines are each connected to a sense amplifier which regulates the potential on the respective bit line to a reference potential and at which an output signal can be picked off. If one of the word lines is selected and all the other word lines are put at reference potential, then the resistance of the resistor, which is assigned to an information item, can be read from the output signal.

    摘要翻译： 电阻器连接在相对于其横向延伸的字线和位线之间。 电阻器具有比字线和位线更高的电阻。 位线各自连接到读出放大器，其将相应位线上的电位调节到参考电位，并且可以在其处拾取输出信号。 如果选择一条字线并且所有其它字线被置于参考电位，则可以从输出信号中读取分配给信息项的电阻的电阻。

    Integrated circuit arrangement with capacitor
    16.
    发明授权
    Integrated circuit arrangement with capacitor 有权
    集成电路布置与电容器

    公开(公告)号：US07291877B2

    公开(公告)日：2007-11-06

    申请号：US10529990

    申请日：2003-10-10

    申请人： Ralf Brederlow ,  Jessica Hartwich ,  Christian Pacha ,  Wolfgang Rösner ,  Thomas Schulz

    发明人： Ralf Brederlow ,  Jessica Hartwich ,  Christian Pacha ,  Wolfgang Rösner ,  Thomas Schulz

    IPC分类号： H01L29/76

    CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/0629 ,  H01L27/108 ,  H01L27/10805 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/1085 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/1211 ,  H01L27/13 ,  H01L28/60 ,  H01L29/66795

    摘要： An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs. Alternately, a FET is present in which: a channel region is the active region, the FET contains a web with opposing control electrodes connected by a connecting region that is isolated from the channel region by a thick insulating region. The thick insulating region is thicker than control electrode insulation regions. The control electrodes contain the same material as the far electrode region.

    摘要翻译： 集成电路装置包括作为平面绝缘层的一部分的绝缘区域和包含：靠近和远离绝缘区域的近远电极区域和电介质区域的电容器。 电容器和有源部件位于绝缘层的同一侧，并且组件的近电极区域和有源区域是平面的并且平行于绝缘层。 近电极区域是单晶体并且包含多个网状物。 或者，存在FET，其中沟道区域是有源区域，FET包含具有相对的控制电极的幅材，该栅极通过由沟道区域与厚绝缘区域隔离的连接区域连接。 厚的绝缘区域比控制电极绝缘区域厚。 控制电极含有与远电极区域相同的材料。

    Integrated circuit arrangement with capacitor and fabrication method
    17.
    发明授权
    Integrated circuit arrangement with capacitor and fabrication method 有权
    具有电容器的集成电路布置及其制造方法

    公开(公告)号：US07820505B2

    公开(公告)日：2010-10-26

    申请号：US11862640

    申请日：2007-09-27

    申请人： Ralf Brederlow ,  Jessica Hartwich ,  Christian Pacha ,  Wolfgang Rösner ,  Thomas Schulz

    发明人： Ralf Brederlow ,  Jessica Hartwich ,  Christian Pacha ,  Wolfgang Rösner ,  Thomas Schulz

    IPC分类号： H01L21/8242

    CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/0629 ,  H01L27/108 ,  H01L27/10805 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/1085 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/1211 ,  H01L27/13 ,  H01L28/60 ,  H01L29/66795

    摘要： An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs. Alternately, a FET is present in which: a channel region is the active region, the FET contains a web with opposing control electrodes connected by a connecting region that is isolated from the channel region by a thick insulating region. The thick insulating region is thicker than control electrode insulation regions. The control electrodes contain the same material as the far electrode region.

    摘要翻译： 集成电路装置包括作为平面绝缘层的一部分的绝缘区域和包含：靠近和远离绝缘区域的近远电极区域和电介质区域的电容器。 电容器和有源部件位于绝缘层的同一侧，并且组件的近电极区域和有源区域是平面的并且平行于绝缘层。 近电极区域是单晶体并且包含多个网状物。 或者，存在FET，其中沟道区域是有源区域，FET包含具有相对的控制电极的幅材，该栅极通过由沟道区域与厚绝缘区域隔离的连接区域连接。 厚的绝缘区域比控制电极绝缘区域厚。 控制电极含有与远电极区域相同的材料。

    Integrated circuit arrangement having capacitors and having planar transistors and fabrication method
    18.
    发明授权
    Integrated circuit arrangement having capacitors and having planar transistors and fabrication method 有权
    具有电容器并具有平面晶体管和制造方法的集成电路装置

    公开(公告)号：US07173302B2

    公开(公告)日：2007-02-06

    申请号：US10531493

    申请日：2003-10-10

    申请人： Ralf Brederlow ,  Jessica Hartwich ,  Christian Pacha ,  Wolfgang Rösner ,  Thomas Schulz

    发明人： Ralf Brederlow ,  Jessica Hartwich ,  Christian Pacha ,  Wolfgang Rösner ,  Thomas Schulz

    IPC分类号： H01L27/108 ,  H01L21/8242

    CPC分类号： H01L27/1085 ,  H01L21/84 ,  H01L27/10805 ,  H01L27/1203

    摘要： An integrated circuit arrangement and method of fabricating the integrated circuit arrangement is described. The integrated circuit arrangement contains an insulating region and a sequence of regions which forms a capacitor. The sequence contains a near electrode region near the insulating region, a dielectric region, and a remote electrode region remote from the insulating region. The insulating region is part of an insulating layer arranged in a plane. The capacitor and an active component are arranged on the same side of the insulating layer and form a memory cell. The near electrode region and an active region of the component are arranged in a plane which lies parallel to the plane in which the insulating layer is arranged. A processor is also contained in the integrated circuit arrangement.

    摘要翻译： 描述了一种集成电路装置及其制造方法。 集成电路装置包含形成电容器的绝缘区域和一系列区域。 该序列包含靠近绝缘区域的近电极区域，电介质区域和远离绝缘区域的远程电极区域。 绝缘区域是布置在平面中的绝缘层的一部分。 电容器和有源部件布置在绝缘层的同一侧上并形成存储单元。 组件的近电极区域和有源区域被布置在与布置绝缘层的平面平行的平面中。 处理器也包含在集成电路装置中。

    Semiconductor memory device
    20.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US08097915B2

    公开(公告)日：2012-01-17

    申请号：US11139976

    申请日：2005-05-31

    申请人： Wolfgang Rösner ,  Franz Hofmann ,  Michael Specht ,  Martin Städele ,  Johannes Luyken

    发明人： Wolfgang Rösner ,  Franz Hofmann ,  Michael Specht ,  Martin Städele ,  Johannes Luyken

    IPC分类号： H01L31/119

    CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L27/1203 ,  H01L29/7393

    摘要： A semiconductor memory device comprises a plurality of memory cells, each memory cell having a respective transistor. The transistor comprises a transistor body of a first conductivity type, a drain area and a source area each having a second conductivity type, wherein said drain area and source area are embedded in the transistor body on a first surface of said transistor body, a gate structure having a gate dielectric layer and a gate electrode. Said gate structure is arranged between said drain area and said source area. An emitter area of said first conductivity type is provided wherein said emitter area is arranged on top of said drain area.

    摘要翻译： 半导体存储器件包括多个存储单元，每个存储单元具有相应的晶体管。 晶体管包括第一导电类型的晶体管体，漏极区域和源极区域，每个具有第二导电类型，其中所述漏极区域和源极区域嵌入在所述晶体管本体的第一表面上的晶体管本体中，栅极 具有栅极电介质层和栅电极的结构。 所述栅极结构布置在所述漏极区域和所述源极区域之间。 提供了所述第一导电类型的发射极区域，其中所述发射极区域布置在所述漏极区域的顶部。