利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

96 条记录 (耗时 0.023 秒)

    Polymer spacers for creating small geometry space and method of manufacture thereof
    12.
    发明授权
    Polymer spacers for creating small geometry space and method of manufacture thereof 有权
    用于产生小几何空间的聚合物间隔物及其制造方法

    公开(公告)号：US06699792B1

    公开(公告)日：2004-03-02

    申请号：US09907398

    申请日：2001-07-17

    申请人： Fei Wang ,  Lu You ,  Lynne Okada

    发明人： Fei Wang ,  Lu You ,  Lynne Okada

    IPC分类号： H01L21311

    CPC分类号： H01L21/32139 ,  H01L21/0271 ,  H01L21/0338 ,  H01L21/31144

    摘要： In forming an opening or space in a substrate, a layer of photoresist is provided on the substrate, and the photoresist is patterned to provide photoresist bodies having respective adjacent sidewalls. A polymer layer is provided on the resulting structure through a low temperature conformal CVD process. The polymer layer is anisotropically etched to form spacers on the respective adjacent sidewalls of the photoresist bodies. The substrate is then etched using the spacers as a mask.

    摘要翻译： 在形成衬底中的开口或空间时，在衬底上提供光致抗蚀剂层，并且对光致抗蚀剂进行图案化以提供具有相应相邻侧壁的光致抗蚀剂体。 通过低温保形CVD工艺在所得结构上提供聚合物层。 聚合物层被各向异性蚀刻以在光致抗蚀剂体的各个相邻侧壁上形成间隔物。 然后使用间隔物作为掩模蚀刻衬底。

    Damascene arrangement for metal interconnection using low k dielectric constant materials for etch stop layer
    15.
    发明授权
    Damascene arrangement for metal interconnection using low k dielectric constant materials for etch stop layer 有权
    用于蚀刻停止层的低k介电常数材料的金属互连的镶嵌装置

    公开(公告)号：US06417090B1

    公开(公告)日：2002-07-09

    申请号：US09225008

    申请日：1999-01-04

    申请人： Fei Wang ,  Lu You

    发明人： Fei Wang ,  Lu You

    IPC分类号： H01L214763

    CPC分类号： H01L21/76802 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/76829

    摘要： A method of forming a damascene structure in a semiconductor device arrangement uses a low k dielectric material in an etch stop layer that overlays a metal interconnect layer. The etch stop layer protects the metal interconnect layer, made of copper, for example, during the etching of a dielectric layer that overlays the etch stop layer. Following the etching of the dielectric layer, which stops on the etch stop layer, the etch stop layer is then etched with a chemistry that does not damage the underlying copper in the metal interconnect layer. The lower dielectric constant material employed in the etch stop layer reduces the overall dielectric constant of the film, thereby improving the operating performance of the chip.

    摘要翻译： 在半导体器件布置中形成镶嵌结构的方法使用覆盖金属互连层的蚀刻停止层中的低k电介质材料。 蚀刻停止层例如在蚀刻覆盖在蚀刻停止层的介电层的蚀刻期间保护由铜制成的金属互连层。 在蚀刻停止层上停止的介电层的蚀刻之后，用不会损坏金属互连层中的下面的铜的化学物质蚀刻蚀刻停止层。 在蚀刻停止层中使用的较低介电常数材料降低了膜的总介电常数，从而提高了芯片的操作性能。

    Method for reduced gate aspect ratio to improve gap-fill after spacer etch
    16.
    发明授权
    Method for reduced gate aspect ratio to improve gap-fill after spacer etch 有权
    减小栅极纵横比以改善间隔物刻蚀之后的间隙填充的方法

    公开(公告)号：US06376309B2

    公开(公告)日：2002-04-23

    申请号：US09811288

    申请日：2001-03-16

    申请人： John JianShi Wang ,  Kent Kuohua Chang ,  Hao Fang ,  Lu You

    发明人： John JianShi Wang ,  Kent Kuohua Chang ,  Hao Fang ,  Lu You

    IPC分类号： H01L29788

    CPC分类号： H01L27/11521 ,  H01L21/76837 ,  H01L27/115

    摘要： The present invention provides a method for reducing the gate aspect ratio of a flash memory device. The method includes forming a tunnel oxide layer on a substrate; forming a polysilicon layer on the tunnel oxide layer; forming an insulating layer on the polysilicon layer; forming a control gate layer on the polysilicon layer; etching at least the tunnel oxide layer, the insulating layer, and the control gate layer to form at least two stack structures; forming a plurality of spacers at sides of the at least two stack structures; and filling at least one gap between the at least two stack structures with an oxide, where the control gate layer provides a gate aspect ratio which allows for a maximum step coverage by the oxide. In a preferred embodiment, the method uses nickel silicide instead of the conventional tungsten silicide in the control gate layers of the cells of the device. Nickel silicide has higher conductivity than conventional silicides, thus a thinner layer of nickel silicide may be used without sacrificing performance. Nickel silicide also has a lower barrier height for holes, thus maintaining a low contact resistance. With a thinner nickel silicide layer, the gate aspect ratio of the cells are lowered, allowing for a maximum step coverage by the gap-filling oxide. The reliability of the device is thus improved.

    摘要翻译： 本发明提供一种降低闪速存储器件的栅极纵横比的方法。 该方法包括在衬底上形成隧道氧化物层; 在隧道氧化层上形成多晶硅层; 在所述多晶硅层上形成绝缘层; 在所述多晶硅层上形成控制栅极层; 至少蚀刻隧道氧化物层，绝缘层和控制栅极层以形成至少两个堆叠结构; 在所述至少两个堆叠结构的侧面处形成多个间隔物; 以及用所述氧化物填充所述至少两个堆叠结构之间的至少一个间隙，其中所述控制栅极层提供允许所述氧化物的最大阶跃覆盖的栅极纵横比。 在优选实施例中，该方法在装置的电池的控制栅极层中使用硅化镍代替常规的硅化钨。 硅化镍具有比常规硅化物更高的导电性，因此可以使用更薄的硅化镍层而不牺牲性能。 硅化镍也具有较低的孔的阻挡高度，因此保持低的接触电阻。 利用更薄的硅化镍层，电池的栅极纵横比降低，允许通过间隙填充氧化物的最大阶梯覆盖。 因此提高了装置的可靠性。

    Dummy patterning for semiconductor manufacturing processes
    17.
    发明授权
    Dummy patterning for semiconductor manufacturing processes 有权
    用于半导体制造工艺的虚拟图案

    公开(公告)号：US06259115B1

    公开(公告)日：2001-07-10

    申请号：US09262214

    申请日：1999-03-04

    申请人： Lu You ,  Simon S. Chan ,  Kai Yang

    发明人： Lu You ,  Simon S. Chan ,  Kai Yang

    IPC分类号： H01L2156

    CPC分类号： H01L21/7684 ,  H01L21/3212 ,  H01L21/76819

    摘要： A method is provided for inserting dummy conductive channels along with the interconnected conductive channels. The dummy channels have an approximately even metal weight distribution to provide better plating uniformity, minimize CMP dishing, improve process heating uniformity, improve spin-on process properties, and increase etch and lithography uniformity.

    摘要翻译： 提供了一种用于将伪导电通道与互连的导电通道一起插入的方法。 虚拟通道具有大致均匀的金属重量分布，以提供更好的电镀均匀性，使CMP凹陷最小化，改善工艺加热均匀性，提高旋涂工艺性能，并增加蚀刻和光刻均匀性。

    Low energy passivation of conductive material in damascene process for semiconductors
    18.
    发明授权
    Low energy passivation of conductive material in damascene process for semiconductors 有权
    半导体镶嵌工艺中导电材料的低能钝化

    公开(公告)号：US06171949B2

    公开(公告)日：2001-01-09

    申请号：US09329155

    申请日：1999-06-09

    申请人： Lu You ,  Shekhar Pramanick

    发明人： Lu You ,  Shekhar Pramanick

    IPC分类号： H01L214763

    CPC分类号： H01L21/76838 ,  H01L21/3143 ,  H01L21/318

    摘要： A method for manufacturing an integrated circuit using damascene processes is provided in which conductive material surfaces subject to chemical-mechanical polishing are passivated after polishing with a dry, low energy, ion implantation passivating process to prevent oxidation and to eliminate a high dielectric constant protective layer. In particular, copper conductive material is subject to nitrogen implantation at or below 100 KeV to produce a protective copper nitride.

    摘要翻译： 提供一种使用镶嵌工艺制造集成电路的方法，其中进行化学机械抛光的导电材料表面在用干燥，低能量的离子注入钝化工艺抛光后被钝化，以防止氧化并消除高介电常数保护层 。 特别地，铜导电材料在100KeV以下进行氮注入以产生保护性的氮化铜。

    Method for improving semiconductor dielectrics
    19.
    发明授权
    Method for improving semiconductor dielectrics 有权
    改善半导体电介质的方法

    公开(公告)号：US06136729A

    公开(公告)日：2000-10-24

    申请号：US133042

    申请日：1998-08-12

    申请人： Dawn M. Hopper ,  Richard J. Huang ,  Lu You

    发明人： Dawn M. Hopper ,  Richard J. Huang ,  Lu You

    IPC分类号： H01L21/312 ,  H01L21/314 ,  H01L21/316 ,  H01L21/31

    CPC分类号： H01L21/02134 ,  H01L21/02282 ,  H01L21/3124 ,  H01L21/316

    摘要： An ultra-large scale integrated circuit is manufactured by using silicon-based, low dielectric materials on a wafer in which the hydrophobic nature of the dielectric materials is improved by relative low temperature heating in a vacuum or inert atmosphere, slowly increasing the wafer temperature to the hard bake temperature at a predetermined ramp rate, and heating the wafer at the hard bake temperature for a predetermine amount of time. As a result, the dielectric material can repel wet etch chemicals and minimize the formation of holes in the dielectric materials due to etching by wet etch chemicals.

    摘要翻译： 通过在晶片上使用硅基低电介质材料制造超大规模集成电路，其中通过在真空或惰性气氛中的相对低温加热来提高电介质材料的疏水性，缓慢地将晶片温度提高到 硬烘烤温度以预定的斜率进行，并且在硬烘烤温度下将晶片加热预定的时间量。 结果，电介质材料可以排斥湿蚀刻化学品，并且由于通过湿蚀刻化学品的蚀刻使介电材料中的孔的形成最小化。