公开(公告)号：US10566348B1

公开(公告)日：2020-02-18

申请号：US16180970

申请日：2018-11-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue

IPC: H01L29/792 ,  H01L27/11582 ,  H01L29/10 ,  H01L23/528 ,  H01L21/8234

Abstract: A memory device comprises a reference conductor, and a stack of conductive strips separated by insulating strips, where the conductive strips in the stack extend in a first direction, and the stack is disposed on the reference conductor. The memory device comprises a plurality of hemi-cylindrical vertical channel structures extending through respective vias in the conductive strips in the stack, and comprising semiconductor films in electrical contact with the reference conductor having outside surfaces. Each of the hemi-cylindrical vertical channel structures has a divided elliptical cross section with a major axis tilted relative to the first direction. The memory device comprises data storage structures between the outside surfaces of the semiconductor films and sidewalls of the vias in the conductive strips.

公开(公告)号：US10535673B2

公开(公告)日：2020-01-14

申请号：US15996617

申请日：2018-06-04

Applicant: Macronix International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Chih-Wei Hu ,  Hang-Ting Lue

IPC: H01L27/11 ,  H01L27/11556 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11565 ,  G11C16/04 ,  G11C11/56 ,  H01L27/11519

Abstract: A memory device that includes: a memory controller; a control unit; and a memory cell array that includes memory blocks, each memory block comprising: memory cells, word lines respectively coupled to the memory cells, signal lines to transfer signals to perform programming operations to one or more memory cells of the memory cells, a first metal layer coupled to a first group of lines and configured to route the first group of the lines to the control unit, the lines comprising the word lines and the signal lines, and a second metal layer coupled to a second group of the lines and configured to route the second group of the lines to the control unit, wherein the memory controller is configured to: control the control unit to (i) select particular memory cells and (ii) program data to the particular memory cells is disclosed.

公开(公告)号：US20180053772A1

公开(公告)日：2018-02-22

申请号：US15290179

申请日：2016-10-11

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue

IPC: H01L27/115 ,  H01L21/28

CPC classification number: H01L27/1157 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66666

Abstract: A memory device is provided. The memory device includes a bottom conductive line, a stacked structure, a side oxide layer, a dielectric layer and a side semiconductor layer. The stacked structure is disposed on the bottom conductive line, and includes a first semiconductor layer, a second semiconductor layer disposed above the first semiconductor layer, and a plurality of oxide layers alternately stacked with the first semiconductor layer and the second semiconductor layer. The side oxide layer is disposed on both side walls of the first conductive layer. The dielectric layer is disposed on the stacked structure. The side semiconductor layer is disposed on the dielectric layer.

公开(公告)号：US09698156B2

公开(公告)日：2017-07-04

申请号：US14637187

申请日：2015-03-03

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue

IPC: G11C16/04 ,  H01L27/11582 ,  H01L29/786 ,  H01L29/51 ,  H01L29/06 ,  H01L29/66 ,  H01L27/11565 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/0649 ,  H01L29/511 ,  H01L29/66742 ,  H01L29/786

Abstract: A memory device which can be configured as a 3D NAND flash memory, includes a plurality of stacks of conductive strips, including even stacks and odd stacks having sidewalls. Some of the conductive strips in the stacks are configured as word lines. Data storage structures are disposed on the sidewalls of the even and odd stacks. Active pillars between corresponding even and odd stacks of conductive strips include even and odd semiconductor films having outside surfaces and inside surfaces, the outside surfaces disposed on the data storage structures on the sidewalls of the corresponding even and odd stacks in the plurality of stacks forming a 3D array of memory cells, the inside surfaces are separated by an insulating structure that can include a gap. The semiconductor films can be thin-films.

公开(公告)号：US09620217B2

公开(公告)日：2017-04-11

申请号：US14668790

申请日：2015-03-25

Applicant: Macronix International Co., Ltd.

Inventor： Hang-Ting Lue ,  Kuo-Pin Chang

IPC: G11C16/14 ,  G11C16/08 ,  G11C16/04 ,  G11C16/16 ,  H01L27/11551 ,  H01L27/11578

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/16 ,  G11C2216/18 ,  H01L27/11551 ,  H01L27/11578

Abstract: A method is provided for operating a NAND array that includes a plurality of blocks of memory cells. A block of memory cells in the plurality of blocks includes a plurality of NAND strings having channel lines between first string select switches and second string select switches. The plurality of NAND strings shares a set of word lines between the first and second string select switches. A channel-side erase voltage is applied to the channel lines through the first string select switches in a selected block. Word line-side erase voltages are applied to a selected subset including more than one member of the set of word lines shared by NAND strings in the selected block to induce tunneling in memory cells coupled to the selected subset, while tunneling is inhibited in memory cells coupled to an unselected subset including more than one member of the set of word lines.

公开(公告)号：US09530503B2

公开(公告)日：2016-12-27

申请号：US14723321

申请日：2015-05-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuo-Pin Chang ,  Hang-Ting Lue

IPC: G11C16/04 ,  G11C16/08

CPC classification number: G11C16/0483 ,  G11C16/08 ,  H01L27/11582

Abstract: A memory device includes a plurality of strings of memory cells. A plurality of stacks of conductive strips includes first upper strips configured as first string select lines for the strings in the plurality of strings, second upper strips configured as second string select lines for the strings in the plurality of strings, and intermediate strips configured as word lines for the strings in the plurality of strings. The memory device includes control circuitry coupled to the first string select lines and the second string select lines, and configured to select a particular string in the plurality of strings by applying a first turn-on voltage to a first string select line in the first string select lines coupled to the particular string, and a second turn-on voltage to a second string select line in the second string select lines coupled to the particular string.

Abstract translation: 存储器件包括多个存储单元串。 导电条的多个堆叠包括构成为多个串中的串的第一串选择线的第一上条，被配置为用于多个字符串中的字符串的第二字符串选择行的第二上条和配置为字的中间条 用于多个字符串中的字符串的行。 存储器件包括耦合到第一串选择线和第二串选择线的控制电路，并且被配置为通过向第一串中的第一串选择线施加第一导通电压来选择多个串中的特定串 选择耦合到特定串的线，以及第二接通电压到耦合到特定串的第二串选择线中的第二串选择线。

公开(公告)号：US09425191B2

公开(公告)日：2016-08-23

申请号：US13965269

申请日：2013-08-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yi-Hsuan Hsiao ,  Yen-Hao Shih ,  Shih-Hung Chen ,  Hang-Ting Lue

IPC: H01L27/06 ,  H01L27/115

CPC classification number: H01L27/0688 ,  H01L27/11531 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578

Abstract: A memory device and a manufacturing method of the same are provided. The memory device includes a substrate, a 3D memory array, a periphery circuit, and a conductive connection structure. The 3D memory array and the periphery circuit are stacked on the substrate. The periphery circuit includes a patterned metal layer and a contact structure electrically connected to the patterned metal layer. The conductive connection structure is electrically connected to the patterned metal layer. The 3D memory array is electrically connected to the periphery circuit via the conductive connection structure.

Abstract translation: 提供了一种存储器件及其制造方法。 存储器件包括衬底，3D存储器阵列，外围电路和导电连接结构。 3D存储器阵列和外围电路堆叠在基板上。 外围电路包括图案化金属层和电连接到图案化金属层的接触结构。 导电连接结构电连接到图案化的金属层。 3D存储器阵列经由导电连接结构电连接到外围电路。

公开(公告)号：US09385184B2

公开(公告)日：2016-07-05

申请号：US14541170

申请日：2014-11-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue

IPC: H01L29/76 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0619 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0642 ,  H01L29/0646

Abstract: A semiconductor device is provided, comprising a substrate; a first well having a first conductive type and extending down from a surface of the substrate; a diffusion region doped with impurity of the first conductive type and extending down from a surface of the first well; and a plurality of active devices formed within the diffusion region, and the active devices arranged separately from each other. The active devices are electrically isolated from each other by the diffusion region. The active device is self-isolated by a conductive guarding structure, and the semiconductor device comprising embodied STI-free active devices solves STI edge issues.

Abstract translation: 提供一种半导体器件，包括：衬底; 第一阱具有第一导电类型并从衬底的表面向下延伸; 掺杂有第一导电类型的杂质并从第一阱的表面向下延伸的扩散区; 以及形成在扩散区域内的多个有源器件，并且有源器件彼此分开布置。 有源器件通过扩散区域彼此电隔离。 有源器件由导电保护结构自隔离，并且包括实施的无STI的有源器件的半导体器件解决STI边缘问题。

公开(公告)号：US20160190270A1

公开(公告)日：2016-06-30

申请号：US14587022

申请日：2014-12-31

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue

IPC: H01L29/423 ,  H01L29/417 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L29/0692 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/78

Abstract: A high voltage (HV) semiconductor device is provided, comprising a substrate, a first well having a first conductive type and extending down from a surface of the substrate; a plurality of active devices respectively formed on the substrate, and the adjacent active devices electrically separated from each other by an insulation. One of the active devices comprises a diffusion region doped with impurity of the first conductive type and extending down from a surface of the first well, a ring gate formed in the diffusion region, and a light doping region having a second conductive type and extending down from a surface of the diffusion region. The light doping region is offset from an edge of the insulation.

Abstract translation: 提供了一种高压（HV）半导体器件，包括：衬底，具有第一导电类型并从衬底的表面向下延伸的第一阱; 分别形成在基板上的多个有源器件，并且相邻的有源器件通过绝缘彼此电分离。 有源器件中的一个包括掺杂有第一导电类型的杂质并从第一阱的表面向下延伸的扩散区，形成在扩散区中的环形栅，以及具有第二导电类型并向下延伸的光掺杂区 从扩散区域的表面。 光掺杂区域从绝缘体的边缘偏移。

公开(公告)号：US09356105B1

公开(公告)日：2016-05-31

申请号：US14584871

申请日：2014-12-29

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue

IPC: H01L27/115 ,  G11C16/04 ,  H01L29/423 ,  G11C16/08 ,  H01L29/792

CPC classification number: H01L29/4234 ,  G11C16/0466 ,  G11C16/0483 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/792

Abstract: A memory device includes a semiconductor body having a first conductivity type, a first terminal in the semiconductor body having a second conductivity type, a channel region having the first conductivity type surrounding the first terminal, and a second terminal having the second conductivity type surrounding the channel region. A connector is in contact with the first terminal, and can be connected to a bit line in an overlying patterned conductor layer. Memory material is disposed over the channel region, and can include a dielectric charge storage structure. A control gate surrounds the first terminal and is disposed over the memory material. A conductive line surrounds the control gate and is in contact with the second terminal. The control gate and the conductive line can be ring shaped.

Abstract translation: 存储器件包括具有第一导电类型的半导体本体，半导体本体中具有第二导电类型的第一端子，具有围绕第一端子的第一导电类型的沟道区域和围绕第一导电类型的第二导电类型的第二端子 渠道区域。 连接器与第一端子接触，并且可以连接到覆盖的图案化导体层中的位线。 存储器材料设置在沟道区域上，并且可以包括介电电荷存储结构。 控制门围绕第一终端并设置在存储器材料之上。 导线围绕控制栅极并与第二端子接触。 控制栅极和导线可以是环形的。