公开(公告)号：US09373526B2

公开(公告)日：2016-06-21

申请号：US14556542

申请日：2014-12-01

Applicant: MediaTek Inc.

Inventor： Wen-Sung Hsu ,  Ming-Chieh Lin ,  Ta-Jen Yu

IPC: H01L21/44 ,  H01L21/48 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/4828 ,  H01L21/481 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49861 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/11912 ,  H01L2224/16238 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81416 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/8146 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01109 ,  H01L2924/012

Abstract: According to an embodiment of the present invention, a method for forming a chip package is provided. The method includes: providing a conducting plate, wherein a plurality of conducting pads are disposed on an upper surface of the conducting plate; forming a plurality of conducting bumps on a lower surface of the conducting plate; patterning the conducting plate by removing a portion of the conducting plate, wherein the patterned conducting plate has a plurality of conducting sections electrically insulated from each other, and each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate; forming an insulating support layer to partially surround the conducting bumps; and disposing a chip on the conducting pads.

Abstract translation: 根据本发明的实施例，提供了一种用于形成芯片封装的方法。 该方法包括：提供导电板，其中多个导电焊盘设置在导电板的上表面上; 在导电板的下表面上形成多个导电凸块; 通过去除导电板的一部分来图案化导电板，其中图案化的导电板具有彼此电绝缘的多个导电部分，并且每个导电凸块电连接到图案化的导电部分的相应一个导电部分 导电板 形成绝缘支撑层以部分地包围所述导电凸块; 并将芯片设置在导电焊盘上。

公开(公告)号：US11469201B2

公开(公告)日：2022-10-11

申请号：US16721475

申请日：2019-12-19

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  Wen-Sung Hsu ,  Ta-Jen Yu ,  Andrew C. Chang

IPC: H01L23/00 ,  H01L49/02 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H01L23/495 ,  H05K3/34

Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.

公开(公告)号：US10573616B2

公开(公告)日：2020-02-25

申请号：US15194658

申请日：2016-06-28

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  Wen-Sung Hsu ,  Ta-Jen Yu ,  Andrew C. Chang

IPC: H01L23/00 ,  H01L49/02 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H01L23/495 ,  H05K3/34

Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.

公开(公告)号：US09972593B2

公开(公告)日：2018-05-15

申请号：US14535643

申请日：2014-11-07

Applicant: MediaTek Inc.

Inventor： Ching-Liou Huang ,  Ta-Jen Yu

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/683 ,  H01L23/31

CPC classification number: H01L24/17 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L2221/68345 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/05022 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16105 ,  H01L2224/16235 ,  H01L2224/17104 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32221 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: The invention provides a semiconductor package. The semiconductor package includes a base having a device-attach surface and a solder-ball attach surface opposite to the device-attach surface. A conductive via is disposed passing through the base. The conductive via includes a first terminal surface aligned to the device-attach surface of the base. A semiconductor die is mounted on the base by a conductive structure. The conductive structure is in contact with the first terminal surface of the conductive via.

公开(公告)号：US09627311B2

公开(公告)日：2017-04-18

申请号：US14602539

申请日：2015-01-22

Applicant: MediaTek Inc.

Inventor： Wen-Sung Hsu ,  Ta-Jen Yu

IPC: H01L23/04 ,  H01L21/44 ,  H01L23/522 ,  H01L23/498 ,  H01L23/50 ,  H01L21/48 ,  H01L27/108 ,  H05K3/32 ,  H05K1/18 ,  H05K3/20

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5384 ,  H01L2224/16227 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/185 ,  H05K3/205 ,  H01L2924/00012 ,  H01L2924/0001

Abstract: A package substrate is provided. The package substrate includes: a dielectric layer; a passive component embedded in the dielectric layer and contacting the dielectric layer; and a circuit layer embedded in the dielectric layer and having a first surface aligned with a second surface of the dielectric layer.

公开(公告)号：US09437457B2

公开(公告)日：2016-09-06

申请号：US14015012

申请日：2013-08-30

Applicant: MediaTek Inc.

Inventor： Wen-Sung Hsu ,  Ming-Chieh Lin ,  Ta-Jen Yu

IPC: H01L23/48 ,  H01L21/48 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/4828 ,  H01L21/481 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49861 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/11912 ,  H01L2224/16238 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81416 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/8146 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01109 ,  H01L2924/012

Abstract: According to an embodiment of the present invention, a chip package is provided. The chip package includes: a patterned conducting plate having a plurality of conducting sections electrically separated from each other; a plurality of conducting pads disposed on an upper surface of the patterned conducting plate; a chip disposed on the conducting pads; a plurality of conducting bumps disposed on a lower surface of the patterned conducting plate, wherein each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate; and an insulating support layer partially surrounding the conducting bumps.

Abstract translation: 根据本发明的实施例，提供了一种芯片封装。 芯片封装包括：图案化导电板，其具有彼此电分离的多个导电部分; 设置在所述图案化导电板的上表面上的多个导电焊盘; 设置在导电垫上的芯片; 设置在所述图案化导电板的下表面上的多个导电凸块，其中每个所述导电凸块电连接到所述图案化导电板的相应一个导电部分; 以及部分地围绕导电凸块的绝缘支撑层。

公开(公告)号：US09177899B2

公开(公告)日：2015-11-03

申请号：US13721983

申请日：2012-12-20

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  Wen-Sung Hsu ,  Ta-Jen Yu ,  Andrew C. Chang

IPC: H01L21/48 ,  H01L21/77 ,  H01L23/495 ,  H01L23/498 ,  H01L23/00 ,  H01L49/02

CPC classification number: H01L23/49541 ,  H01L21/48 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L28/00 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2924/12042 ,  Y10T29/41 ,  H01L2224/05571 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.

Abstract translation: 本发明提供半导体封装和用于制造用于半导体封装的基座的方法。 半导体封装包括嵌入基座中的导电迹线。 半导体器件通过导电结构安装在导电迹线上。

公开(公告)号：US10916449B2

公开(公告)日：2021-02-09

申请号：US16743866

申请日：2020-01-15

Applicant: MediaTek Inc.

Inventor： Wen-Sung Hsu ,  Ta-Jen Yu

IPC: H01L23/64 ,  H01L23/538 ,  H01L23/66 ,  H01L21/48 ,  H01L25/00 ,  H01L23/498 ,  H01L23/00 ,  H05K1/18 ,  H05K3/00 ,  H05K3/10 ,  H05K3/18 ,  H05K3/30 ,  H01F17/00 ,  H01L21/683 ,  H01L21/70 ,  H01L21/56 ,  H05K1/16

Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a base. The base has a device-attach surface. A radio-frequency (RF) device is embedded in the base. The RF device is close to the device-attach surface.

公开(公告)号：US20200176408A1

公开(公告)日：2020-06-04

申请号：US16721475

申请日：2019-12-19

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  Wen-Sung Hsu ,  Ta-Jen Yu ,  Andrew C. Chang

IPC: H01L23/00 ,  H01L23/495 ,  H05K1/11 ,  H01L21/48 ,  H01L23/498 ,  H01L49/02

Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.

公开(公告)号：US10580747B2

公开(公告)日：2020-03-03

申请号：US14205880

申请日：2014-03-12

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  Wen-Sung Hsu ,  Ta-Jen Yu ,  Andrew C. Chang

IPC: H01L23/00 ,  H01L49/02 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H01L23/495 ,  H05K3/34

Abstract: In one configuration, a semiconductor package includes a conductive trace embedded in a base and a semiconductor device mounted on the conductive trace via a conductive structure, wherein the conductive structure is a bump structure and the width of the bump structure is bigger than the width of the conductive trace. In another configuration, a method for fabricating a semiconductor package includes providing a base, forming at least one conductive trace on the base, forming an additional insulation material on the base, and defining patterns upon the additional insulation material, wherein the pattern is formed on at least one conductive trace, wherein the conductive structure is a bump structure and the width of the bump structure is bigger than the width of the conductive trace.