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    Integrated Assemblies and Methods of Forming Integrated Assemblies
    11.
    发明申请
    Integrated Assemblies and Methods of Forming Integrated Assemblies 有权

    公开(公告)号：US20220246634A1

    公开(公告)日：2022-08-04

    申请号：US17162524

    申请日：2021-01-29

    Applicant: Micron Technology, Inc.

    Inventor： Alyssa N. Scarbrough ,  Jordan D. Greenlee ,  John D. Hopkins

    IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573

    Abstract: Some embodiments include an integrated assembly having a memory region and another region adjacent the memory region. Channel-material-pillars are arranged within the memory region, and conductive posts are arranged within said other region. A source structure is coupled to lower regions of the channel-material-pillars. A panel extends across the memory region and the other region. Doped-semiconductor-material is directly adjacent to the panel within the memory region and the other region. The doped-semiconductor-material is at least part of the source structure within the memory region. Liners are directly adjacent to the conductive posts and laterally surround the conductive posts. The liners are between the conductive posts and the doped-semiconductor-material. Some embodiments include methods of forming integrated assemblies.

    Memory Array Comprising Strings Of Memory Cells And Method Used In Forming A Memory Array Comprising Strings Of Memory Cells
    12.
    发明申请
    Memory Array Comprising Strings Of Memory Cells And Method Used In Forming A Memory Array Comprising Strings Of Memory Cells 有权

    公开(公告)号：US20220246628A1

    公开(公告)日：2022-08-04

    申请号：US17162062

    申请日：2021-01-29

    Applicant: Micron Technology, Inc.

    Inventor： Alyssa N. Scarbrough ,  John D. Hopkins

    IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/06 ,  H01L23/522 ,  H01L21/48

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions. Simultaneously, (a), (b), and (c) are formed, where (a): horizontally-elongated trenches into the stack laterally-between immediately-laterally-adjacent of the memory-block regions; (b): channel openings into the stack laterally-between the horizontally-elongated trenches; and (c): through-array-via (TAV) openings into the stack in a stair-step region. Intervening material is formed in the horizontally-elongated trenches, a channel-material string in individual of the channel openings, and conductive material in the TAV openings. Other aspects, including structure independent of method, are disclosed.

    Memory array comprising strings of memory cells and conductive gate lines of different vertical thicknesses
    14.
    发明授权
    Memory array comprising strings of memory cells and conductive gate lines of different vertical thicknesses 有权

    公开(公告)号：US12277973B2

    公开(公告)日：2025-04-15

    申请号：US18588407

    申请日：2024-02-27

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins ,  Alyssa N. Scarbrough

    IPC: H10B41/27 ,  G11C16/04 ,  H01L21/28 ,  H01L29/423 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers comprising laterally-spaced memory-block regions having horizontally-elongated trenches there-between. Two of the first tiers have different vertical thicknesses relative one another. Channel-material strings of memory cells extend through the first tiers and the second tiers. Through the horizontally-elongated trenches, first conductive material is formed in void space in the two first tiers. The first conductive material fills the first tier of the two first tiers that has a smaller of the different vertical thicknesses in individual of the memory-block regions. The first conductive material less-than-fills the first tier of the two first tiers that has a larger of the different vertical thicknesses in the individual memory-block regions. Through the horizontally-elongated trenches, the first conductive material is isotropically etched from the first tier having the larger vertical thickness in the individual memory-block regions to leave the first conductive material in the first tier having the smaller vertical thickness in the individual memory-block regions. After the isotropically etching of the first conductive material and through the horizontally-elongated trenches, second conductive material is formed in the first tier having the larger vertical thickness in the individual memory-block regions. Other embodiments, including structure independent of method, are disclosed.

    Staircase formation in a memory array
    15.
    发明授权
    Staircase formation in a memory array 有权

    公开(公告)号：US12245426B2

    公开(公告)日：2025-03-04

    申请号：US17822712

    申请日：2022-08-26

    Applicant: Micron Technology, Inc.

    Inventor： Alyssa N. Scarbrough ,  Lifang Xu ,  Jordan D. Greenlee

    IPC: H10B43/20 ,  G11C16/08 ,  H01L21/768 ,  H10B43/35

    Abstract: Methods, systems, and devices for staircase formation in a memory array are described. A first liner material may be deposited on a tread above a first contact surface and a portion of the first liner material may be doped. A second liner material may be deposited over the first liner and a portion of the second liner material may be doped. After doping the portions of the liner materials, the undoped portions of the liner materials may be removed so that the materials above a second contact surface can be at least partially removed via a first removal process. The doped portion of the first liner material may then be cut back so that a second removal process can expose the second contact surface and a third contact (while the first contact surface is protected from the removal process by the liner materials).

    Memory Circuitry And Method Used In Forming Memory Circuitry
    18.
    发明公开
    Memory Circuitry And Method Used In Forming Memory Circuitry 审中-公开

    公开(公告)号：US20240074183A1

    公开(公告)日：2024-02-29

    申请号：US17897516

    申请日：2022-08-29

    Applicant: Micron Technology, Inc.

    Inventor： John D. Hopkins ,  Alyssa N. Scarbrough

    IPC: H01L27/11582 ,  H01L23/535 ,  H01L27/11556

    CPC classification number: H01L27/11582 ,  H01L23/535 ,  H01L27/11556

    Abstract: Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a flight of stairs extending along a first direction. Multiple different-depth treads in individual of the stairs extend along a second direction that is orthogonal to the first direction. Individual of the multiple different-depth treads comprise conducting material of one of the conductive tiers. The multiple different-depth treads in the individual stairs comprise a first flight of the treads and a second flight of the treads. A landing is between and lower in the stack than each of the first and second flights of treads. The first and second flights of treads in the second direction face toward one another. Methods are disclosed.

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