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    Memory array with an air gap between memory cells and the formation thereof
    13.
    发明授权
    Memory array with an air gap between memory cells and the formation thereof 有权
    存储器阵列与存储单元之间的空气间隙及其形成

    公开(公告)号：US08716084B2

    公开(公告)日：2014-05-06

    申请号：US13902052

    申请日：2013-05-24

    Applicant: Micron Technology, Inc.

    Inventor： Andrew Bicksler ,  Christopher J. Larsen

    IPC: H01L21/336 ,  H01L29/66

    CPC classification number: H01L29/66825 ,  H01L21/764 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/66833

    Abstract: A method of forming a memory array includes forming a dielectric over a semiconductor, forming a charge-storage structure over the dielectric, forming an isolation region through the dielectric and the charge-storage structure and extending into the semiconductor, recessing the isolation region to a level below a level of an upper surface of the dielectric and at or above a level of an upper surface of the semiconductor, forming an access line over the charge-storage structure and the recessed isolation region, and forming an air gap over the recessed isolation region so that the air gap passes through the charge-storage structure, so that the air gap extends to and terminates at a bottom surface of the access line, and so that the entire air gap is between the bottom surface of the access line and the upper surface of the semiconductor.

    Abstract translation: 形成存储器阵列的方法包括在半导体上形成电介质，在电介质上形成电荷存储结构，通过电介质和电荷存储结构形成隔离区并延伸到半导体中，使隔离区凹陷到 电平低于电介质的上表面的电平并且在半导体的上表面的水平以上，在电荷存储结构和凹陷隔离区域上形成存取线，并且在凹陷隔离件上形成气隙 区域，使得气隙通过电荷存储结构，使得气隙延伸到并终止于进入管线的底表面，并且使得整个气隙位于进入管线的底表面和 半导体的上表面。

    Memory devices including gate leakage transistors
    15.
    发明授权
    Memory devices including gate leakage transistors 有权

    公开(公告)号：US11869590B2

    公开(公告)日：2024-01-09

    申请号：US17458954

    申请日：2021-08-27

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Andrew Bicksler ,  Marc Aoulaiche

    IPC: G11C16/04 ,  G11C16/16 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

    CPC classification number: G11C16/0483 ,  G11C16/16 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

    Abstract: A memory device includes a string of series-connected memory cells, a data line, a first select transistor, a common source, a second select transistor, and a gate leakage transistor. The string of series-connected memory cells includes a vertical channel region. Each memory cell of the string of series-connected memory cells includes a first gate stack structure. The data line is connected to the vertical channel region. The first select transistor is connected between the data line and the string of series-connected memory cells. The second select transistor is connected between the common source and the string of series-connected memory cells. The gate leakage transistor is connected between the first select transistor and the second select transistor. The gate leakage transistor includes a second gate stack structure different from the first gate stack structure.

    DYNAMIC STEP VOLTAGE LEVEL ADJUSTMENT
    16.
    发明申请
    DYNAMIC STEP VOLTAGE LEVEL ADJUSTMENT 有权

    公开(公告)号：US20230133227A1

    公开(公告)日：2023-05-04

    申请号：US17939273

    申请日：2022-09-07

    Applicant: Micron Technology, Inc.

    Inventor： Carmine Miccoli ,  Andrew Bicksler

    IPC: G11C16/12 ,  G11C16/10 ,  G11C16/08

    Abstract: Processing logic in a memory device receives a request to execute a programming operation on a set of memory cells of the memory device. A first set of programming pulses corresponding to a first step voltage level are caused to be applied to one or more wordlines associated with the set of memory cells. The processing logic determines that a programming voltage level associated with a programming pulse of the first set of programming pulses satisfies a condition. A second set of programming pulses corresponding to a second step voltage level is caused to be applied to the one or more wordlines associated with the set of memory cells in response to the condition being satisfied.

    Sense flags in a memory device
    17.
    发明授权
    Sense flags in a memory device 有权

    公开(公告)号：US10409506B2

    公开(公告)日：2019-09-10

    申请号：US16117348

    申请日：2018-08-30

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Shafqat Ahmed ,  Khaled Hasnat ,  Pranav Kalavade ,  Krishna Parat ,  Aaron Yip ,  Mark A. Helm ,  Andrew Bicksler

    IPC: G06F3/06 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G06F12/0804 ,  G06F13/28 ,  G06F12/0846

    Abstract: Methods for programming sense flags may include programming memory cells coupled to first data lines in a main memory array, and programming memory cells coupled to second data lines in the main memory array while programming memory cells coupled to data lines in a flag memory array with flag data indicative of the memory cells coupled to the second data lines being programmed. Methods for sensing flags may include performing a sense operation on memory cells coupled to first data lines of a main memory array and memory cells coupled to data lines of a flag memory array, and determining a program indication of memory cells coupled to second data lines of the main memory array from the sense operation performed on the memory cells coupled to the data lines of the flag memory array.

    Methods and apparatuses having strings of memory cells including a metal source
    19.
    发明授权
    Methods and apparatuses having strings of memory cells including a metal source 有权
    具有包括金属源的存储单元串的方法和装置

    公开(公告)号：US09437604B2

    公开(公告)日：2016-09-06

    申请号：US14069553

    申请日：2013-11-01

    Applicant: Micron Technology, Inc.

    Inventor： Zhenyu Lu ,  Roger W. Lindsay ,  Andrew Bicksler ,  Yongjun J Hu ,  Haitao Liu

    IPC: H01L21/336 ,  H01L27/115 ,  H01L29/66 ,  H01L29/792

    CPC classification number: H01L27/11556 ,  H01L23/5283 ,  H01L27/11524 ,  H01L29/456 ,  H01L29/66825 ,  H01L29/7926

    Abstract: Methods for forming a string of memory cells, an apparatus having a string of memory cells, and a system are disclosed. A method for forming the string of memory cells comprises forming a metal silicide source material over a substrate. The metal silicide source material is doped. A vertical string of memory cells is formed over the metal silicide source material. A semiconductor material is formed vertically and adjacent to the vertical string of memory cells and coupled to the metal silicide source material.

    Abstract translation: 公开了形成一串存储器单元的方法，具有一串存储单元的装置和系统。 一种用于形成存储单元串的方法包括在衬底上形成金属硅化物源材料。 掺杂金属硅化物源材料。 在金属硅化物源材料上形成垂直的存储单元串。 半导体材料垂直地形成并且与垂直的存储单元串相邻并且耦合到金属硅化物源材料。

    SEMICONDUCTOR DEVICE STRUCTURES AND MEMORY DEVICES INCLUDING A UNIFORM PATTERN OF CONDUCTIVE MATERIAL
    20.
    发明申请
    SEMICONDUCTOR DEVICE STRUCTURES AND MEMORY DEVICES INCLUDING A UNIFORM PATTERN OF CONDUCTIVE MATERIAL 有权
    半导体器件结构和存储器件，包括导电材料的均匀图案

    公开(公告)号：US20130175695A1

    公开(公告)日：2013-07-11

    申请号：US13781027

    申请日：2013-02-28

    Applicant: Micron Technology, Inc.

    Inventor： Andrew Bicksler

    IPC: H01L23/48

    CPC classification number: H01L23/48 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods of forming semiconductor device structures are disclosed. One method comprises forming a plurality of loops of a conductive material. Each loop of the plurality of loops comprises a uniform pattern. In one embodiment, a portion of the conductive material is removed from at least one location in each loop of the plurality of loops. Contacts are formed to the conductive material. A semiconductor device structure is also disclosed.

    Abstract translation: 公开了形成半导体器件结构的方法。 一种方法包括形成导电材料的多个环。 多个回路中的每个回路包括均匀的图案。 在一个实施例中，导电材料的一部分从多个环的每个环中的至少一个位置移除。 触点形成为导电材料。 还公开了半导体器件结构。

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