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    METHODS OF MAKING AN INTERPOSER STRUCTURE WITH EMBEDDED CAPACITOR STRUCTURE
    14.
    发明申请
    METHODS OF MAKING AN INTERPOSER STRUCTURE WITH EMBEDDED CAPACITOR STRUCTURE 有权
    使用嵌入式电容器结构制造插入式结构的方法

    公开(公告)号：US20140162412A1

    公开(公告)日：2014-06-12

    申请号：US14180567

    申请日：2014-02-14

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Chin Hui Chong ,  David J. Corisis ,  Choon Kuan Lee

    IPC: H01L21/48 ,  H01L49/02 ,  H01L23/00

    CPC classification number: H01L21/4857 ,  H01L23/50 ,  H01L24/82 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

    Abstract: A device is disclosed which includes an interposer, at least one capacitor formed at least partially within an opening formed in the interposer and an integrated circuit that is operatively coupled to the interposer. A method is disclosed which includes obtaining an interposer having at least one capacitor formed at least partially within an opening in the interposer and operatively coupling an integrated circuit to the interposer. A method is also disclosed which includes obtaining an interposer comprising a dielectric material, forming an opening in the interposer and forming a capacitor that is positioned at least partially within the opening.

    Abstract translation: 公开了一种包括插入器的至少一个电容器，至少部分地形成在插入器中形成的开口内的至少一个电容器和可操作地耦合到插入器的集成电路。 公开了一种方法，其包括获得具有至少部分地在插入器中的开口内形成的至少一个电容器并且将集成电路可操作地耦合到插入器的插入器。 还公开了一种方法，其包括获得包括电介质材料的插入件，在插入器中形成开口并形成至少部分位于开口内的电容器。

    BUILD-UP PACKAGE FOR INTEGRATED CIRCUIT DEVICES, AND METHODS OF MAKING SAME
    17.
    发明申请
    BUILD-UP PACKAGE FOR INTEGRATED CIRCUIT DEVICES, AND METHODS OF MAKING SAME 有权

    公开(公告)号：US20230005802A1

    公开(公告)日：2023-01-05

    申请号：US17843799

    申请日：2022-06-17

    Applicant: Micron Technology, Inc.

    Inventor： Hong Wan Ng ,  Choon Kuan Lee ,  David J. Corisis ,  Chin Hui Chong

    IPC: H01L23/18 ,  H01L23/00 ,  H01L23/373 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78

    Abstract: A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.

    Build-up package for integrated circuit devices, and methods of making same
    18.
    发明授权
    Build-up package for integrated circuit devices, and methods of making same 有权

    公开(公告)号：US11367667B2

    公开(公告)日：2022-06-21

    申请号：US16819486

    申请日：2020-03-16

    Applicant: Micron Technology, Inc.

    Inventor： Hong Wan Ng ,  Choon Kuan Lee ,  David J. Corisis ,  Chin Hui Chong

    IPC: H01L23/18 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L23/373 ,  H01L21/78

    Abstract: A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.

    NOVEL BUILD-UP PACKAGE FOR INTEGRATED CIRCUIT DEVICES, AND METHODS OF MAKING SAME
    20.
    发明申请
    NOVEL BUILD-UP PACKAGE FOR INTEGRATED CIRCUIT DEVICES, AND METHODS OF MAKING SAME 审中-公开

    公开(公告)号：US20200286801A1

    公开(公告)日：2020-09-10

    申请号：US16819486

    申请日：2020-03-16

    Applicant: Micron Technology, Inc.

    Inventor： Hong Wan Ng ,  Choon Kuan Lee ,  David J. Corisis ,  Chin Hui Chong

    IPC: H01L23/18 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L23/373

    Abstract: A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.

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