公开(公告)号：US20190279689A1

公开(公告)日：2019-09-12

申请号：US16426435

申请日：2019-05-30

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Stefano Ratti ,  Gary G. Lazarowics ,  Stefan Frederik Schippers ,  Stefano Claudio Roseghini ,  Angelo Clemente Scardilla

IPC: G11C7/04 ,  G06F3/06 ,  G01K3/00 ,  G11C13/00 ,  G11C16/34 ,  G11C16/26

Abstract: Apparatuses, methods, and devices that can be utilized to provide temperature-based memory operations are described. One or more apparatuses can include a memory device and a controller coupled to the memory device and configured to: determine an operating temperature of the apparatus, determine one of a plurality of designated open blocks of the memory device to write data based on the operating temperature of the apparatus and a size of the data, and write the data in the determined one of the plurality of designated blocks of the memory device.

公开(公告)号：US10261876B2

公开(公告)日：2019-04-16

申请号：US15345862

申请日：2016-11-08

Applicant: Micron Technology, Inc.

Inventor： Marco Dallabora ,  Emanuele Confalonieri ,  Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio

IPC: G06F11/20 ,  G06F3/06

Abstract: The present disclosure includes apparatuses and methods related to hybrid memory management. An example apparatus can include a first memory array, a number of second memory arrays, and a controller coupled to the first memory array and the number of second memory arrays configured to execute a write operation, wherein execution of the write operation writes data to the first memory array starting at a location indicated by a write cursor, and place the write cursor at an updated location in the first memory array upon completing execution of the write operation, wherein the updated location is a next available location in the first memory array.

公开(公告)号：US10162556B2

公开(公告)日：2018-12-25

申请号：US15685926

申请日：2017-08-24

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Emanuele Confalonieri ,  Federico Tiziani

IPC: G06F3/06 ,  G06F12/02 ,  G06F13/38 ,  G06F9/50 ,  G11C14/00 ,  G11C13/00

Abstract: Various embodiments comprise devices and methods to manage multiple memory types and reconfigure partitions in a memory device as directed by a host. In one embodiment, the device is to manage logical memory partitioning on each of multiple memory devices that are based on differing, hybrid-memory technologies, the device is further to hide an actual storage media type of the multiple memory devices from the host through abstracted logical interface blocks. Additional devices and methods are described.

公开(公告)号：US09880772B2

公开(公告)日：2018-01-30

申请号：US14860326

申请日：2015-09-21

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Graziano Mirichigni ,  Gianfranco Santopietro ,  Gianfranco Ferrante ,  Emanuele Confalonieri

IPC: G06F3/06

CPC classification number: G06F3/0643 ,  G06F3/061 ,  G06F3/0679

Abstract: A memory device includes a memory component and controller circuitry. The memory component stores data and the controller circuitry receives, from a host electronic device, one or more commands of a memory system protocol. The one or more commands include at least one write command, the write command comprising one or more blocks of data to be stored in the memory component. Further, the one or more commands include metadata, attributes, or both related to the one or more blocks of data. The controller circuitry interprets and executes the one or more commands. Accordingly, the blocks are stored in the memory component. Further, the controller circuitry of the memory device has access to the metadata, attributes or both.

公开(公告)号：US09529736B2

公开(公告)日：2016-12-27

申请号：US14932503

申请日：2015-11-04

Applicant: Micron Technology, Inc.

Inventor： Giulio Albini ,  Emanuele Confalonieri

IPC: G06F12/14 ,  G06F3/06 ,  G06F12/00 ,  G06F13/40 ,  G06F13/42 ,  G06F13/16

CPC classification number: G06F12/1466 ,  G06F3/0622 ,  G06F3/0637 ,  G06F3/0673 ,  G06F3/0679 ,  G06F12/00 ,  G06F12/14 ,  G06F13/1668 ,  G06F13/4036 ,  G06F13/4221 ,  G06F2212/1052

Abstract: Subject matter disclosed herein relates to an apparatus comprising memory and a controller, such as a controller which determines block locking states in association with operative transitions between two or more interfaces that share at least one block of memory. The apparatus may support single channel or multi-channel memory access, write protection state logic, or various interface priority schemes.

公开(公告)号：US20140223087A1

公开(公告)日：2014-08-07

申请号：US14247783

申请日：2014-04-08

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Emanuele Confalonieri ,  Federico Tiziani

IPC: G06F9/50 ,  G11C14/00 ,  G06F12/02

CPC classification number: G06F3/0644 ,  G06F3/0607 ,  G06F3/0608 ,  G06F3/0631 ,  G06F3/0637 ,  G06F3/0685 ,  G06F9/5077 ,  G06F12/0223 ,  G06F12/0238 ,  G06F12/0246 ,  G06F13/385 ,  G06F2212/2022 ,  G06F2212/2024 ,  G06F2213/3804 ,  G06F2213/3854 ,  G11C13/0002 ,  G11C13/0004 ,  G11C14/009 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described.

Abstract translation: 各种实施例包括装置和方法，包括如由主机指导的在存储器装置中重新配置分区的方法。 该方法包括通过第一接口控制器管理命令以映射不具有属性增强集合的第一存储器的部分，以及通过第二接口控制器映射具有属性增强集合的第二存储器的部分。 描述附加的装置和方法。

公开(公告)号：US20140149823A1

公开(公告)日：2014-05-29

申请号：US14166724

申请日：2014-01-28

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Sara Villa

IPC: G06F11/10 ,  H03M13/11

CPC classification number: G06F11/1008 ,  G06F11/1068 ,  G06F11/1072 ,  G11C2029/0411 ,  H03M13/1105

Abstract: Embodiments of the present disclosure provide methods, systems, and apparatuses related to calculating an error correction code for a program page dependent on guard values that correspond to words of the program page. Other embodiments may be described and claimed.

Abstract translation: 本公开的实施例提供了与根据与节目页的单词相对应的保护值来计算用于节目页的纠错码相关的方法，系统和装置。 可以描述和要求保护其他实施例。

公开(公告)号：US20250130720A1

公开(公告)日：2025-04-24

申请号：US18903468

申请日：2024-10-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Marco Sforzin ,  Emanuele Confalonieri

IPC: G06F3/06

Abstract: A system includes a memory device; and a processing device coupled to the memory device, the processing device to perform operations including: identifying at least one unusable management unit (UMU) in a plurality of management units that are designated for wear leveling; storing, in a data structure, a physical address and a logical address of the identified at least one UMU; excluding, from a physical address space for wear leveling, the physical address of the identified at least one UMU; and performing a wear leveling operation using the physical address space, wherein the wear leveling operation moves data of a management unit to a neighboring management unit in a circular manner.

公开(公告)号：US20250094344A1

公开(公告)日：2025-03-20

申请号：US18782380

申请日：2024-07-24

Applicant: Micron Technology, Inc.

Inventor： Rishabh Dubey ,  Marco Sforzin ,  Emanuele Confalonieri ,  Danilo Caraccio ,  Daniele Balluchi ,  Nicola Del Gatto

IPC: G06F12/02 ,  G06F13/16

Abstract: A variety of applications can include a memory device having chained mapping with compression of received data. The memory device can include a mapping table having an entry location to associate a virtual page with a physical address of a first stripe of compressed data of the virtual page. A controller of the memory device, responsive to the data of the virtual page being compressed data, can load information about a second stripe of the compressed data into extra locations in the first stripe different from locations for compressed data of the virtual page in the first stripe. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US12124729B2

公开(公告)日：2024-10-22

申请号：US17687018

申请日：2022-03-04

Applicant: Micron Technology, Inc.

Inventor： Nicola Del Gatto ,  Federica Cresci ,  Emanuele Confalonieri

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/061 ,  G06F3/0673

Abstract: Systems, apparatuses, and methods related to a controller for managing metrics and telemetry are described. A controller includes a front end portion, a central controller portion, a back end portion, and a management unit. The central controller portion can include a cache to store data associated with the performance of the memory operations, metric logic configured to collect metrics related to performance of the memory operations, load telemetry logic configured to collect load telemetry associated with performance of the memory operations within a threshold time, and a storage area to store the collected metrics and the collected load telemetry. The management unit memory of the controller can store metrics and load telemetry associatAND ed with monitoring the characteristics of the memory controller, and based on the stored metrics and load telemetry, alter at least one characteristic of the computing system.