公开(公告)号：US20240177755A1

公开(公告)日：2024-05-30

申请号：US18388032

申请日：2023-11-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeffrey S. McNeil ,  Eric N. Lee ,  Tomoko Ogura Iwasaki ,  Sheyang Ning ,  Lawrence Celso Miranda ,  Kishore Kumar Muchherla

IPC: G11C11/00 ,  G06F12/02 ,  G11C16/04

CPC classification number: G11C11/005 ,  G06F12/0246 ,  G11C16/0483

Abstract: Memories might include an array of memory cells having a plurality of strings of series-connected memory cells and a controller configured to cause to memory to access a first string of series-connected memory cells of the plurality of strings of series-connected memory cells in a first mode of operation for volatile storage of data to the first string of series-connected memory cells, and access a second string of series-connected memory cells of the plurality of strings of series-connected memory cells in a second mode of operation for non-volatile storage of respective data to each memory cell of a plurality of memory cells of the second string of series-connected memory cells

公开(公告)号：US11977778B2

公开(公告)日：2024-05-07

申请号：US17691014

申请日：2022-03-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kishore Kumar Muchherla ,  Eric N. Lee ,  Jeffrey S. McNeil ,  Jonathan S. Parry ,  Lakshmi Kalpana Vakati

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679

Abstract: A method performed by a processing device receives a plurality of write operation requests, where each of the write operation requests specifies a respective one of the memory units, identifies one or more operating characteristic values, where each operating characteristic value reflects one or more memory access operations performed on a memory device, and determines whether the operating characteristic values satisfy one or more threshold criteria. Responsive to determining that the operating characteristic values satisfy the one or more threshold criteria, the method performs a plurality of write operations, where each of the write operations writes data to the respective one of the memory units, and performs a multiple-read scan operation subsequent to the plurality of write operations, where the multiple-read scan operation reads data from each of the memory units.

公开(公告)号：US20240069765A1

公开(公告)日：2024-02-29

申请号：US17894794

申请日：2022-08-24

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Robert Loren O. Ursua ,  Sead Zildzic ,  Eric N. Lee ,  Jonathan S. Parry ,  Lakshmi Kalpana K. Vakati ,  Jeffrey S. McNeil

IPC: G06F3/06

CPC classification number: G06F3/0629 ,  G06F3/0625 ,  G06F3/0679

Abstract: A system can include a processing device operatively coupled with the one or more memory devices, to perform operations that include writing data to the one or more memory devices and performing one or more scan operations on a management unit containing the data to determine a current value of a chosen data state metric. Each scan operation can be performed using a corresponding predetermined read-time parameter value. The operations can include determining whether the current value of the chosen data state metric satisfies a criterion, and can also include, responsive to determining that the current value of the chosen data state metric satisfies the criterion, selecting a remedial operation by determining whether redundancy metadata is included in a fault tolerant data stripe on the one or more memory devices. The operations can also include performing the remedial operation with respect to the management unit.

公开(公告)号：US11887680B2

公开(公告)日：2024-01-30

申请号：US17873716

申请日：2022-07-26

Applicant: Micron Technology, Inc.

Inventor： Jeffrey S. McNeil ,  Jason Lee Nevill ,  Tommaso Vali

IPC: G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G06F3/06 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C2211/5621

Abstract: Over time, the number of write cycles required to successfully program a multi-level cell (MLC) is reduced. Since a hard-coded value does not change over the lifetime of the device, the device may perform too many verify steps at one stage of the device lifetime and wait too long to begin verification at another stage of the device lifetime, reducing performance of the device. As discussed herein, verification for higher voltage level programming is delayed until verification for lower voltage level programming reaches at least a threshold level of success instead of using a hard-coded number of verify steps to skip. As a result, the performance drawbacks associated with skipping a hard-coded number of verify cycles may not occur.

公开(公告)号：US20230307055A1

公开(公告)日：2023-09-28

申请号：US18121846

申请日：2023-03-15

Applicant: Micron Technology, Inc.

Inventor： Lawrence Celso Miranda ,  Tomoko Ogura Iwasaki ,  Sheyang Ning ,  Jeffrey S. McNeil

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

Abstract: Described are systems and methods for concurrent slow-fast memory cell programming. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying a set of memory cells for performing a memory programming operation, wherein the set of memory cells are electrically coupled to a target wordline and one or more target bitlines; causing a first programming pulse to be performed by applying a first programming voltage to the target wordline; classifying, by a processing device, the set of memory cells into a first subset of memory cells and a second subset of memory cells based on their respective threshold voltages; causing a first bias voltage to be applied to a first target bitline connected to the first subset of memory cells; causing a second bias voltage to be applied to a second target bitline connected to the second subset of memory cells; and causing a second programing voltage to be applied to the target wordline, wherein the second programming voltage exceeds the first programing voltage.

公开(公告)号：US20230307053A1

公开(公告)日：2023-09-28

申请号：US18119997

申请日：2023-03-10

Applicant: Micron Technology, Inc.

Inventor： Paing Z. Htet ,  Akira Goda ,  Eric N. Lee ,  Jeffrey S. McNeil ,  Junwyn A. Lacsao ,  Kishore Kumar Muchherla ,  Sead Zildzic ,  Violante Moschiano

IPC: G11C16/08 ,  G11C16/26 ,  G11C16/10 ,  G11C16/04

CPC classification number: G11C16/08 ,  G11C16/26 ,  G11C16/102 ,  G11C16/0433

Abstract: A memory array includes a block including wordlines, bitlines, and strings each connected to a respective bitline. The block is divided into a sub-blocks. Each sub-block includes a respective set of the strings, and each string of the set of strings is located at a sub-block position within its respective sub-block. Control logic performs operations including selecting each sub-block, causing a first voltage to be applied to a dummy wordline to activate a first set of dummy cells and deactivate a second set of dummy cells, and causing a second voltage to be applied to a selected wordline. Each sub-block includes a single string corresponding to an open string connected to a dummy cell of the first set of dummy cells. The second voltage causes data to be read out from each open string to a respective page buffer.

公开(公告)号：US20230195350A1

公开(公告)日：2023-06-22

申请号：US17715799

申请日：2022-04-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Peter Feeley ,  Jonathan S. Parry ,  Akira Goda ,  Jeffrey S. McNeil

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/065 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G06F12/0253

Abstract: A first set of host data items are programmed to first memory pages residing at a first region of a memory sub-system. A second set of host data items are programmed to second memory pages residing at the first region. A determination is made that a sequence at which the first set of host data items and the second set of host data items are programmed does not correspond to a target sequence associated with the memory sub-system. One or more of the first set of host data items are copied from one or more first memory pages to a second region of the memory sub-system that is allocated to store host data items initially programmed to first memory pages at the memory sub-system. One or more of the second set of host data items are copied from one or more second memory pages to a third region of the memory sub-system to store host data items that are programmed to second pages at the memory sub-system. A sequence of the copied one or more of the first set of host data items at the second region and the copied one or more of the second set of host data items at the third region correspond to the target sequence.

公开(公告)号：US20230062445A1

公开(公告)日：2023-03-02

申请号：US17682089

申请日：2022-02-28

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Violante Moschiano ,  Jeffrey S. McNeil ,  James Fitzpatrick ,  Sivagnanam Parthasarathy ,  Kishore Kumar Muchherla ,  Patrick R. Khayat

IPC: G11C16/30 ,  G11C16/10 ,  G11C16/26

Abstract: Processing logic in a memory device receives a command to execute a set of read operations having read voltage levels corresponding to a programming distribution associated with the memory device. A set of memory bit counts is determined, where each memory bit count corresponds to a respective bin of a set of bins associated with the multiple read voltage levels of the set of read operations. A valley center bin having a minimum memory bit count of the set of memory bit counts is determined. The processing logic determines that the minimum memory bit count of the valley center bin satisfies a condition and an adjusted read voltage level associated with the valley center bin is identified in response to the condition being satisfied.

公开(公告)号：US20200258574A1

公开(公告)日：2020-08-13

申请号：US16861435

申请日：2020-04-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeffrey S. McNeil

IPC: G11C16/08 ,  G11C16/04

Abstract: Apparatus configured to perform an access operation on a memory cell of an array of memory cells, discharge a control gate of a first field-effect transistor after performing the access operation, discharge a control gate of a second field-effect transistor connected in series between the first field-effect transistor and the memory cell after discharging the control gate of the first field-effect transistor, and discharge a control gate of the memory cell after discharging the control gate of the second field-effect transistor.

公开(公告)号：US20250028447A1

公开(公告)日：2025-01-23

申请号：US18906876

申请日：2024-10-04

Applicant: Micron Technology, Inc.

Inventor： Jeremy Binfet ,  Violante Moschiano ,  James Fitzpatrick ,  Kishore Kumar Muccherla ,  Jeffrey S. McNeil ,  Phong Sy Nguyen

IPC: G06F3/06

Abstract: A memory device includes an array of memory cells associated with a plurality of wordlines and control logic operatively coupled with the array of memory cells. The control logic can receive a program command comprising a digital value indicating that a physical address of the program command corresponds to a retired wordline of the plurality of wordlines. The control logic can generate dummy data in response to detecting the digital value within the program command. The memory logic can cause the dummy data to be programmed to memory cells that are selectively coupled to the retired wordline.