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公开(公告)号：US11853558B2
公开(公告)日：2023-12-26
申请号：US17718386
申请日：2022-04-12
发明人： David A. Palmer , Jonathan S. Parry , Reshmi Basu
IPC分类号： G06F3/06
CPC分类号： G06F3/0617 , G06F3/0653 , G06F3/0679
摘要： Apparatuses and methods can be related power down workload estimations using artificial neural networks. Workload estimation can include predicting a duration of a subsequent power down event of the memory device. A quantity of maintenance operations to be performed on the memory device, may be predicted based on the predicted duration of the subsequent power down event, when the memory device is powered on after the subsequent power down event using an artificial neural network. The quantity of maintenance operations may be performed on the memory device prior to the subsequent power down event of the memory device.
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公开(公告)号：US20230393756A1
公开(公告)日：2023-12-07
申请号：US17863000
申请日：2022-07-12
发明人： Kishore Kumar Muchherla , Jonathan S. Parry , Nicola Ciocchini , Animesh Roy Chowdhury , Akira Goda , Jung Sheng Hoei , Niccolo' Righetti , Ugo Russo
IPC分类号： G06F3/06
CPC分类号： G06F3/0619 , G06F3/0679 , G06F3/0653
摘要： A system includes a memory device including multiple memory cells and a processing device operatively coupled to the memory device. The processing device is to receive a first read command at a first time. The first read command is with respect to a set of memory cells of the memory device. The processing device is further to receive a second read command at a second time. The second read command is with respect to the set of memory cells of the memory device. The processing device is further to increment a read counter for the memory device by a value reflecting a difference between the first time and the second time. The processing device is further to determine that a value of the read counter satisfies a threshold criterion. The processing device is further to perform a data integrity scan with respect to the set of memory cells.
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13.发明授权公开(公告)号：US11742028B2
公开(公告)日：2023-08-29
申请号：US18053201
申请日：2022-11-07
IPC分类号： G11C16/14 , G11C16/30 , G11C17/16 , G11C17/18 , G11C16/22 , G11C13/00 , G11C11/16 , G11C11/22 , G11C16/08
CPC分类号： G11C16/14 , G11C11/165 , G11C11/1653 , G11C11/1675 , G11C11/1697 , G11C11/225 , G11C11/2253 , G11C11/2275 , G11C11/2297 , G11C13/0004 , G11C13/0023 , G11C13/0038 , G11C13/0059 , G11C13/0097 , G11C16/08 , G11C16/22 , G11C16/30 , G11C17/165 , G11C17/18
摘要： Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.
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公开(公告)号：US11720261B2
公开(公告)日：2023-08-08
申请号：US16989596
申请日：2020-08-10
发明人： Qing Liang , Nadav Grosz , Jonathan S. Parry , Deping He
IPC分类号： G06F3/06
CPC分类号： G06F3/0625 , G06F3/0623 , G06F3/0653 , G06F3/0659 , G06F3/0679
摘要： Methods, systems, and devices for transferring memory system data to a host system are described. A system may be configured for transferring information between a memory system and a host system in response to transitions between various operating modes, such as operating modes associated with different operating power levels. For example, before entering a reduced power mode, the memory system may identify information stored in a volatile memory array and transmit the identified information to the host system. Such information transmitted to the host system may be returned to the memory system to support memory system operation after exiting the reduced power mode. In some examples, such information exchanged between the memory system and the host system may be associated with a processing capability of the memory system, and the described operations may be referred to as suspending memory system processing information to a host system.
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公开(公告)号：US11704252B2
公开(公告)日：2023-07-18
申请号：US17495410
申请日：2021-10-06
CPC分类号： G06F12/10 , G11C16/0483 , G11C16/10 , G11C16/26 , G06F2212/657 , G11C2216/14
摘要： Methods, systems, and devices for dual address encoding for logical-to-physical mapping are described. A memory device may identify a first physical address corresponding to a first logical block address generated by a host device and a second physical address corresponding to a second (consecutive) logical block address generated by a host device. The memory device may store the first physical address and second physical address in a single entry of a logical-to-physical mapping table that corresponds to the first logical block address. The memory device may transmit the logical-to-physical table to the host device for storage at the host device. The host device may subsequently transmit a single read command to the memory device that includes the first physical address and the second physical address based on the logical-to-physical table.
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公开(公告)号：US20230214126A1
公开(公告)日：2023-07-06
申请号：US17718386
申请日：2022-04-12
发明人： David A. Palmer , Jonathan S. Parry , Reshmi Basu
IPC分类号： G06F3/06
CPC分类号： G06F3/0617 , G06F3/0653 , G06F3/0679
摘要： Apparatuses and methods can be related power down workload estimations using artificial neural networks. Workload estimation can include predicting a duration of a subsequent power down event of the memory device. A quantity of maintenance operations to be performed on the memory device, may be predicted based on the predicted duration of the subsequent power down event, when the memory device is powered on after the subsequent power down event using an artificial neural network. The quantity of maintenance operations may be performed on the memory device prior to the subsequent power down event of the memory device.
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公开(公告)号：US11656940B2
公开(公告)日：2023-05-23
申请号：US17574059
申请日：2022-01-12
发明人： Deping He , Chun Sum Yeung , Jonathan S. Parry
CPC分类号： G06F11/1068 , G06F3/064 , G06F3/0619 , G06F3/0659 , G06F3/0679 , G06F11/076 , G06F11/0772
摘要： Methods, systems, and devices for techniques for managing temporarily retired blocks of a memory system are described. In some examples, aspects of a memory system or memory device may be configured to determine an error for a block of memory cells. For example, a controller may determine an existence of the error and may temporarily retire the block. A media management operation may be performed on the temporarily retired block and, depending on one or more characteristics of the error, the temporarily retired block may be enabled or retired.
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公开(公告)号：US20230137736A1
公开(公告)日：2023-05-04
申请号：US18048364
申请日：2022-10-20
IPC分类号： G06F12/1009
摘要： Methods, systems, and devices for compressed logical-to-physical mapping for sequentially stored data are described. A memory device may use a hierarchical set of logical-to-physical mapping tables for mapping logical block address generated by a host device to physical addresses of the memory device. The memory device may determine whether all of the entries of a terminal logical-to-physical mapping table are consecutive physical addresses. In response to determining that all of the entries contain consecutive physical addresses, the memory device may store a starting physical address of the consecutive physical addresses as an entry in a higher-level table along with a flag indicating that the entry points directly to data in the memory device rather than pointing to a terminal logical-to-physical mapping table. The memory device may, for subsequent reads of data stored in one or more of the consecutive physical addresses, bypass the terminal table to read the data.
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公开(公告)号：US11605434B1
公开(公告)日：2023-03-14
申请号：US17462305
申请日：2021-08-31
发明人： Jonathan S. Parry , Jeffrey S. McNeil , Giuseppe Cariello , Kishore Kumar Muchherla , Reshmi Basu
摘要： Methods, systems, and devices for overwriting at a memory system are described. A memory system may be configured to overwrite portions of a memory array with new data, which may be associated with omitting an erase operation. For example, write operations may be performed in accordance with a first demarcation configuration to store information at a portion of a memory array. A portion of a memory system may then determine to overwrite the portion of the memory array with different or updated information, which may include performing write operations in accordance with a second demarcation configuration. The second demarcation configuration may be associated with different cell characteristics for a one or more logic states, such as different distributions of stored charge or other cell property, different demarcation characteristics, different write operations, among other differences, which may support performing an overwrite operation without first performing an erase operation.
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公开(公告)号：US20230068580A1
公开(公告)日：2023-03-02
申请号：US17672026
申请日：2022-02-15
发明人： Chang H. Siau , Jonathan S. Parry
IPC分类号： G06F3/06
摘要： A memory device including a first plane group comprising a first plane, a second plane group comprising a second plane, a first input/output (I/O) interface configured to access the first plane group, and a second I/O interface configured to access the second plane group. The memory device further includes a controller operatively coupled to the first I/O interface via a first channel and operatively coupled to the second I/O interface via a second channel. The controller can transmit, via the first channel to the first I/O interface, a first command to execute a first memory access operation associated with the first plane. The controller can transmit, via the second channel to the second I/O interface, a second command to execute a second memory access operation associated with the second plane.
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