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    APPARATUSES AND METHODS FOR DIE SEAL CRACK DETECTION
    11.
    发明申请
    APPARATUSES AND METHODS FOR DIE SEAL CRACK DETECTION 有权
    DIE密封破裂检测的装置和方法

    公开(公告)号：US20150170979A1

    公开(公告)日：2015-06-18

    申请号：US14106190

    申请日：2013-12-13

    Applicant: Micron Technology, Inc.

    Inventor： Charles H. Dennison ,  Kenneth W. Marr ,  Deepak Thimmegowda ,  Philip J. Ireland

    IPC: H01L21/66

    CPC classification number: G01R31/2896 ,  H01L22/14 ,  H01L22/34 ,  H01L23/48 ,  H01L23/481 ,  H01L23/485 ,  H01L29/7823 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Apparatuses and methods can include a die seal between an integrated circuit region of a die and a periphery of the die. A via chain(s) may be arranged around an inner circumference of the die seal between the die seal and the integrated circuit region and/or around an outer circumference of the die seal between the die seal and the periphery of the die. The via chain may include a plurality of contacts comprised of conductive material and extending through portions of the die. Circuitry may be coupled to an end of the via chain to detect an electrical signal. Additional apparatuses and methods are described.

    Abstract translation: 设备和方法可以包括在管芯的集成电路区域和管芯周边之间的管芯密封。 通孔链可围绕模具密封件和集成电路区域之间的模具密封件的内圆周和/或围绕模具密封件和模具周边之间的模具密封件的外圆周布置。 通孔链可以包括多个由导电材料组成并且延伸穿过模具的部分的触点。 电路可以耦合到通孔链的端部以检测电信号。 描述附加的装置和方法。

    MEMORY SYSTEM FAILURE DETECTION AND SELF RECOVERY OF MEMORY DICE
    12.
    发明公开
    MEMORY SYSTEM FAILURE DETECTION AND SELF RECOVERY OF MEMORY DICE 审中-公开

    公开(公告)号：US20230393955A1

    公开(公告)日：2023-12-07

    申请号：US17877779

    申请日：2022-07-29

    Applicant: Micron Technology, Inc.

    Inventor： Robert Mason ,  Scott A. Stoller ,  Pitamber Shukla ,  Kenneth W. Marr ,  Chi Ming Chu ,  Hossein Afkhami

    IPC: G06F11/14 ,  G06F9/30

    CPC classification number: G06F11/1471 ,  G06F9/30098 ,  G06F11/1469

    Abstract: Exemplary methods, apparatuses, and systems including memory self-recovery management to correct failures due to soft-error rate events. The self-recovery manager detects a failure of a memory device. The self-recovery manager retrieves a set of register values from the memory device. The self-recovery manager stores the set of register values from the memory device. The self-recovery manager issues a reset command to the memory device, the reset command including generating a re-initialized set of register values. The self-recovery manager compares the set of register values with the re-initialized set of register values. The self-recovery manager triggering a self-recovery attempt using the comparison of the set of register values with the re-initialized set of register values.

    ACTIVE PROTECTION CIRCUITS FOR SEMICONDUCTOR DEVICES
    14.
    发明公开
    ACTIVE PROTECTION CIRCUITS FOR SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20230275042A1

    公开(公告)日：2023-08-31

    申请号：US18142992

    申请日：2023-05-03

    Applicant: Micron Technology, Inc.

    Inventor： Michael A. Smith ,  Kenneth W. Marr

    IPC: H01L23/60 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

    CPC classification number: H01L23/60 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

    Abstract: Active protection circuits for semiconductor devices, and associated systems and methods, are disclosed herein. The active protection circuits may protect various components of the semiconductor devices from process induced damage—e.g., stemming from process charging effects. In some embodiments, the active protection circuit includes an FET and a resistor coupled to certain nodes (e.g., source plates for 3D NAND memory arrays) of the semiconductor devices, which may be prone to accumulate the process charging effects. The active protection circuits prevent the nodes from reaching a predetermined voltage during process steps utilizing charged particles. Subsequently, metal jumpers may be added to the active protection circuits to deactivate the FETs for normal operations of the semiconductor devices. Further, the FET and the resistor of the active protection circuit may be integrated with an existing component of the semiconductor device.

    Apparatuses and methods for die seal crack detection
    17.
    发明授权
    Apparatuses and methods for die seal crack detection 有权
    模具密封裂纹检测的装置和方法

    公开(公告)号：US09557376B2

    公开(公告)日：2017-01-31

    申请号：US15069316

    申请日：2016-03-14

    Applicant: Micron Technology, Inc.

    Inventor： Charles H. Dennison ,  Kenneth W. Marr ,  Deepak Thimmegowda ,  Philip J. Ireland

    IPC: G01R31/28 ,  H01L21/66 ,  H01L23/48 ,  H01L23/485 ,  H01L29/78

    CPC classification number: G01R31/2896 ,  H01L22/14 ,  H01L22/34 ,  H01L23/48 ,  H01L23/481 ,  H01L23/485 ,  H01L29/7823 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Apparatuses and methods can include a die seal between an integrated circuit region of a die and a periphery of the die. A via chain(s) may be arranged around an inner circumference of the die seal between the die seal and the integrated circuit region and/or around an outer circumference of the die seal between the die seal and the periphery of the die. The via chain may include a plurality of contacts comprised of conductive material and extending through portions of the die. Circuitry may be coupled to an end of the via chain to detect an electrical signal. Additional apparatuses and methods are described.

    Abstract translation: 设备和方法可以包括在管芯的集成电路区域和管芯周边之间的管芯密封。 通孔链可围绕模具密封件和集成电路区域之间的模具密封件的内圆周和/或围绕模具密封件和模具周边之间的模具密封件的外圆周布置。 通孔链可以包括多个由导电材料组成并且延伸穿过模具的部分的触点。 电路可以耦合到通孔链的端部以检测电信号。 描述附加的装置和方法。

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