公开(公告)号：US12029032B2

公开(公告)日：2024-07-02

申请号：US18117989

申请日：2023-03-06

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H10B41/35 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3215 ,  H01L21/67 ,  H01L21/768 ,  H10B20/00 ,  H10B41/20 ,  H10B41/23 ,  H10B41/27 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/35 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/3215 ,  H01L21/32155 ,  H01L21/67063 ,  H01L21/76802 ,  H10B20/383 ,  H10B41/20 ,  H10B41/23 ,  H10B41/27 ,  H10B43/27 ,  H01L2221/1063 ,  H10B43/35

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20240063068A1

公开(公告)日：2024-02-22

申请号：US17892036

申请日：2022-08-19

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Bret K. Street ,  Terrence B. McDaniel ,  Jaekyu Song

IPC: H01L23/13 ,  H01L25/065 ,  H01L25/00 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L23/13 ,  H01L25/0652 ,  H01L25/50 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/5382 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/73

Abstract: A semiconductor device assembly comprises a package substrate including (i) an upper surface having a plurality of internal contacts, (ii) a lower surface having a plurality of external contacts coupled to the plurality of internal contacts, and (iii) a cavity extending into the package substrate. The assembly further comprises a stack of first semiconductor devices disposed in the cavity, an uppermost first semiconductor device of the stack having a plurality of stack contacts, and an interposer including (i) a bottom surface having a first plurality of lower contacts coupled to the plurality of stack contacts and a second plurality of lower contacts coupled to the plurality of internal contacts, and (ii) a top surface having a plurality of upper contacts coupled to the first and second pluralities of lower contacts. The assembly further comprises a second semiconductor device including a plurality of die contacts coupled to the plurality of upper contacts.

公开(公告)号：US20230317518A1

公开(公告)日：2023-10-05

申请号：US18333235

申请日：2023-06-12

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L21/76877 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53228 ,  H01L21/76802 ,  H10B41/27 ,  H10B43/27

Abstract: A method of forming a microelectronic device comprises forming line structures comprising conductive material and insulative material overlying the conductive material, the line structures separated from one another by trenches. An isolation material is formed on surfaces of the line structures inside and outside of the trenches, the isolation material only partially filling the trenches to form air gaps interposed between the line structures. Openings are formed to extend through the isolation material and expose portions of the insulative material of the line structures. The exposed portions of the insulative material of the line structures are removed to form extended openings extending to the conductive material of the line structures. Conductive contact structures are formed within the extended openings. Conductive pad structures are formed on the conductive contact structures. Additional methods, microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20230284452A1

公开(公告)日：2023-09-07

申请号：US18196039

申请日：2023-05-11

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H10B43/27 ,  H01L29/06 ,  H01L21/768 ,  H01L21/02 ,  H01L21/762 ,  H10B41/27

CPC classification number: H10B43/27 ,  H01L29/0649 ,  H01L21/76877 ,  H01L21/02164 ,  H01L21/76224 ,  H01L21/0217 ,  H10B41/27

Abstract: Some embodiments include an integrated assembly having a conductive structure which includes a semiconductor material over a metal-containing material. A stack of alternating conductive levels and insulative levels is over the conductive structure. A partition extends through the stack. The partition has wall regions, and has corner regions where two or more wall regions meet. The conductive structure includes a first portion which extends directly under the corner regions, and includes a second portion which is directly under the wall regions and is not directly under the corner regions. The first portion has a first thickness of the semiconductor material and the second portion has a second thickness of the semiconductor material. The first thickness is greater than the second thickness. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230260877A1

公开(公告)日：2023-08-17

申请号：US17670393

申请日：2022-02-11

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Kyle K. Kirby ,  Bret K. Street ,  Kunal R. Parekh

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L24/16 ,  H01L25/0657 ,  H01L21/76898 ,  H01L2225/06541

Abstract: A semiconductor device having monolithic conductive cylinders, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor substrate, a conductive pad, an opening, and a top dielectric layer. The conductive pad may be at a first surface of the semiconductor substrate. The opening may be ring-shaped and extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the top dielectric layer may cover the second surface and may fill the opening. A second ring-shaped opening may be formed through the semiconductor device and the opening and a conductive material plated therein.

公开(公告)号：US20230139914A1

公开(公告)日：2023-05-04

申请号：US17719198

申请日：2022-04-12

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H01L23/373 ,  H01L25/065 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00

Abstract: A semiconductor device assembly is provided. The assembly includes a first semiconductor device including a plurality of electrical contacts on an upper surface thereof; a monolithic silicon structure having a lower surface in contact with the upper surface of the first semiconductor device, the monolithic silicon structure including a cavity extending from the lower surface into a body of the monolithic silicon structure; and a second semiconductor device disposed in the cavity and including a plurality of interconnects, each operatively coupled to a corresponding one of the plurality of electrical contacts.

公开(公告)号：US20230051235A1

公开(公告)日：2023-02-16

申请号：US17885291

申请日：2022-08-10

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Glen E. Hush ,  Sean S. Eilert ,  Aliasger T. Zaidy

IPC: H01L21/66 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L21/78 ,  H01L25/00

Abstract: A wafer-on-wafer bonded memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. Memory devices can be formed on a first wafer. First metal pads can be formed on the first wafer and coupled to the memory devices. The memory devices can be tested via the first metal pads. The first metal pads can be removed from the first wafer. Subsequently, second metal pads on the first wafer can be bonded, via a wafer-on-wafer bonding process, to third metal pads on a second wafer. Each memory device on the first wafer can be aligned with and coupled to a respective logic device on the second wafer.

公开(公告)号：US20230046050A1

公开(公告)日：2023-02-16

申请号：US17830981

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Glen E. Hush ,  Aliasger T. Zaidy ,  Kunal R. Parekh

IPC: G11C7/10 ,  G11C7/08 ,  H01L23/00 ,  H01L25/065

Abstract: A memory device includes a memory die bonded to a logic die via a wafer-on-wafer bond. A controller of the memory device that is coupled to the memory die can activate a row of the memory die. Responsive to activating the row, a sense amplifier stripe of the memory die can latch a first plurality of signals. A transceiver can route a second plurality of signals from the sense amplifier stripe to the logic die.

公开(公告)号：US20220246681A1

公开(公告)日：2022-08-04

申请号：US17165746

申请日：2021-02-02

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H01L27/24 ,  G11C5/06 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573 ,  H01L45/00 ,  H01L25/18 ,  H01L25/16

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a first control logic region comprising first control logic devices, and a first memory array region vertically overlying the first control logic region and comprising an array of vertically extending strings of memory cells. An additional microelectronic device structure comprising a semiconductive material is attached to an upper surface of the microelectronic device structure. A portion of the semiconductive material is removed. A second control logic region is formed over the first memory array region. The second control logic region comprises second control logic devices and a remaining portion of the semiconductive material. A second memory array region is formed over the second control logic region. The second memory array region comprises an array of resistance variable memory cells. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US11335602B2

公开(公告)日：2022-05-17

申请号：US16905763

申请日：2020-06-18

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H01L21/8234 ,  H01L21/768 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure; a doped semiconductive material overlying the base structure; a stack structure overlying the doped semiconductive material; semiconductive structures extending from within the base structure, through the doped semiconductive structure, and into a lower portion of the stack structure; cell pillar structures horizontally aligned with the semiconductive structures and vertically extending through an upper portion of the stack structure; and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form an assembly. The base structure and portions of the semiconductive structures are removed. The doped semiconductive material is then patterned to form at least one source structure coupled to the cell pillar structures. Devices and systems are also described.